ADT7411ARQ 데이터 시트보기 (PDF) - Analog Devices
부품명
상세내역
일치하는 목록
ADT7411ARQ Datasheet PDF : 36 Pages
| |||
ADT7411
SECOND READ
COMMAND
MSB
REGISTER
OUTPUT
DATA
UNLOCK ASSOCIATED
MSB REGISTERS
Figure 30. Phase 2 of 10-Bit Read
If an MSB register is read first, its corresponding LSB register is
not locked out, thus leaving the user with the option of just
reading back 8 bits (MSB) of a 10-bit conversion result. Reading
an MSB register first does not lock out other MSB registers, and
likewise reading an LSB register first does not lock out other
LSB registers.
Table 7. ADT7411 Registers
RD/WR
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h-17h
18h
19h
1Ah
1Bh-1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h-2Ah
2Bh
2Ch
2Dh
Name
Interrupt Status 1
Interrupt Status 2
Reserved
Internal Temperature and VDD LSBs
External Temperature and AIN1 to AIN 4 LSBs
AIN5 to AIN8 LSBs
VDD MSBs
Internal Temperature MSBs
External Temperature MSBs/AIN1 MSBs
AIN2 MSBs
AIN3 MSBs
AIN4 MSBs
AIN5 MSBs
AIN6 MSBs
AIN7 MSBs
AIN8 MSBs
Reserved
Control Configuration 1
Control Configuration 2
Control Configuration 3
Reserved
Interrupt Mask 1
Interrupt Mask 2
Internal Temperature Offset
External Temperature Offset
Reserved
Reserved
VDD VHIGH Limit
VDD VLOW Limit
Internal THIGH Limit
Internal TLOW Limit
External THIGH/AIN1 VHIGH Limits
External TLOW/AIN1 VLOW Limits
Reserved
AIN2 VHIGH Limit
AIN2 VLOW Limit
AIN3 VHIGH Limit
Power-
on
Default
00h
00h
00h
00h
00h
xxh
00h
00h
00h
00h
00h
00h
00h
00h
00h
08h
00h
00h
00h
00h
00h
00h
C7h
62h
64h
C9h
FFh
00h
FFh
00h
FFh
RD/WR
Address
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h-4Ch
4Dh
4Eh
4Fh
50h-7Eh
7F
80hn-FFh
Name
AIN3 VLOW Limit
AIN4 VHIGH Limit
AIN4 VLOW Limit
AIN5 VHIGH Limit
AIN5 VLOW Limit
AIN6 VHIGH Limit
AIN6 VLOW Limit
AIN7 VHIGH Limit
AIN7 VLOW Limit
AIN8 VHIGH Limit
AIN8 VLOW Limit
Reserved
Device ID
Manufacturer’s ID
Silicon Revision
Reserved
SPI Lock Status
Reserved
Power-
on
Default
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
02h
41h
xxh
00h
00h
00h
Interrupt Status 1 Register (Read-Only) [Address = 00h]
This 8-bit read-only register reflects the status of some of the
interrupts that can cause the INT/INT pin to go active. This
register is reset by a read operation provided that any out-of-
limit event is corrected. It is also reset by a software reset.
Table 8. Interrupt Status 1 Register
D7 D6 D5 D4 D3 D2 D1 D0
01
01
01
01
01
01
01
01
1 Default settings at power-up.
Rev. B | Page 20 of 36
Share Link: 