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ADP3158

4-Bit Programmable Synchronous Buck Controllers

Analog Devices 

ADP3158/ADP3178

FROM CPU

3.3V

C15

1␮F

R2

10k⍀

VLR1

2.5V, 2A

Q1*

C1 +

100␮F

ADP3158/

ADP3178

1 VID0

GND 16

2 VID1

DRVH 15

3 VID2 U1 DRVL 14

4 VID3

VCC 13

C2 5 LRFB1

LRFB2 12

68pF 6 LRDRV1 LRDRV2 11

7 CS–

8 CS+

COMP 10

CT 9

C3

150pF

R4

220⍀

C10

R3

1nF

220⍀

+ C6

1␮F

D2

MBR052LT1

D3

MBR052LT1

L2

1␮H

+ C7

22␮F

+ C8

+ C9

1000␮F

1000␮F

5V STANDBY

12V

5V

RA

78.7k⍀

RB

10.5k⍀

COC

2.7nF

Q4*

Q3**

L1

1.7␮H

R12

4m⍀

1000␮F ؋ 5

24m⍀ (EACH)

VCC CORE

1.30V TO

+ + + + + 2.05V

15A

C17 C18 C19 C20 C21

C11

68pF 3.3V

C12

1␮F

Q2*

+ C2

100␮F

R11

10k⍀

VLR2

1.8V,

2A

*SUB45N03-13L

**SUB75N03-07

Figure 3. 15 A Pentium III Application Circuit

The linear regulator controllers have been designed so that they

remain active even when the switching controller is in UVLO mode

to ensure that the output voltages of the linear regulators will track

the 3.3 V supply as required by Intel design specifications. By

diode ORing the VCC input of the IC to the 5 VSB and 12 V

supplies as shown in Figure 3, the switching output will be disabled

in standby mode, but the linear regulators will begin conducting

once VCC rises above about 1 V. During start-up the linear out-

puts will track the 3.3 V supply up until they reach their respective

regulation points, regardless of the state of the 12 V supply. Once

the 12 V supply has exceeded the 5 VSB supply by more than a

diode drop, the controller IC will track the 12 V supply. Once the

12 V supply has risen above the UVLO value, the switching regula-

tor will begin its start-up sequence.

VID3

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

Table I. Output Voltage vs. VID Code

VID2

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

VID1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

VID0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VOUT(NOM)

1.30 V

1.35 V

1.40 V

1.45 V

1.50 V

1.55 V

1.60 V

1.65 V

1.70 V

1.75 V

1.80 V

1.85 V

1.90 V

1.95 V

2.00 V

2.05 V

APPLICATION INFORMATION

Specifications for a Design Example

The design parameters for a typical 750 MHz Pentium III appli-

cation (shown in Figure 3) are as follows:

Input Voltage: (VIN) = 5 V

Auxiliary Input: (VCC) = 12 V

Output Voltage (VVID) = 1.7 V

Maximum Output Current (IO(MAX)) = 15 A

Minimum Output Current (IO(MIN)) = 1 A

Static tolerance of the supply voltage for the processor core

(∆VO) = +40 mV (–80 mV) = 120 mV

Transient tolerance (for less than 2 µs) of the supply voltage

for the processor core when the load changes between the

minimum and maximum values with a di/dt of 20 A/µs

(∆VO(TRANSIENT)) = +80 mV (–130 mV) = 210 mV

Input current di/dt when the load changes between the mini-

mum and maximum values < 0.1 A/µs.

The above requirements correspond to Intel’s published power

supply requirements based on VRM 8.4 guidelines.

–6–

REV. A

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