ADIS16203(Rev0) 데이터 시트보기 (PDF) - Analog Devices
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ADIS16203 Datasheet PDF : 28 Pages
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ADIS16203
TIMING SPECIFICATIONS
TA = +25°C, VDD = 3.3 V, tilt = 0°, unless otherwise noted.
Table 2.
Parameter
fSCLK
tDATARATE
tCS
tDAV
tDSU
tDHD
tDF
tDR
tSFS
Description
Fast mode, SMPL_TIME ≤ 0x07 (fS ≥ 1024 Hz)
Normal mode, SMPL_TIME ≥ 0x08 (fS ≤ 910 Hz)
Chip select period, fast mode, SMPL_TIME ≤ 0x07 (fS ≥ 1024 Hz)
Chip select period, normal mode, SMPL_TIME ≥ 0x08 (fS ≤ 910 Hz)
Chip select to clock edge
Data output valid after SCLK falling edge2
Data input setup time before SCLK rising edge
Data input hold time after SCLK rising edge
Data output fall time
Data output rise time
CS high after SCLK edge3
Min1
0.01
0.01
40
100
48.8
24.4
48.8
5
Typ
Max
Unit
2.5
MHz
1.0
MHz
μs
μs
ns
100
ns
ns
ns
5
12.5
ns
5
12.5
ns
ns
1 Guaranteed by design, not production tested.
2 The MSB presents an exception to this parameter. The MSB clocks out on the falling edge of CS. The rest of the DOUT bits are clocked after the falling edge of SCLK and are
governed by this specification.
3 This parameter may need to be expanded to allow for proper capture of the LSB. After CS goes high, the DOUT line goes into a high impedance state.
TIMING DIAGRAMS
CS
tDATARATE
tSTALL
SCLK
tSTALL = tDATARATE – 16/fSCLK
Figure 2. SPI Chip Select Timing
CS
SCLK
DOUT
DIN
tCS
1
MSB
W/R
2
3
4
5
6
tDAV
DB14
tDSU
DB13
DB12
tDHD
DB11
DB10
A5
A4
A3
A2
15
16
tSFS
DB2
DB1
LSB
D2
D1
LSB
Figure 3. SPI Timing, Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1
Rev. 0 | Page 5 of 28
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