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ADF4360-9BCPZRL7

Clock Generator PLL with Integrated VCO

Analog Devices 

ADF4360-9

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 16. SW1 and SW2

are normally closed switches, and SW3 is normally open. When

power-down is initiated, SW3 is closed, and SW1 and SW2 are

opened. This ensures that there is no loading of the REFIN pin at

power-down.

POWER-DOWN

CONTROL

NC 100kΩ

REFIN NC

SW2

SW1

SW3

NO

TO R COUNTER

BUFFER

Figure 16. Reference Input Stage

N COUNTER

The CMOS N counter allows a wide division ratio in the PLL

feedback counter. The counters are specified to work when the

VCO output is 400 MHz or less. To avoid confusion, this is

referred to as the B counter. It makes it possible to generate

output frequencies that are spaced only by the reference

frequency divided by R. The VCO frequency equation is

fVCO = B × fREFIN/R

where:

fVCO is the output frequency of the VCO.

B is the preset divide ratio of the binary 13-bit counter (3 to 8191).

fREFIN is the external reference frequency oscillator.

R COUNTER

The 14-bit R counter allows the input reference frequency

to be divided down to produce the reference clock to the phase

frequency detector (PFD). Division ratios from 1 to 16,383 are

allowed.

PFD AND CHARGE PUMP

The PFD takes inputs from the R counter and N counter (N = B)

and produces an output proportional to the phase and frequency

difference between them. Figure 17 is a simplified schematic.

The PFD includes a programmable delay element that controls

the width of the antibacklash pulse. This pulse ensures that

there is no dead zone in the PFD transfer function and

minimizes phase noise and reference spurs. Two bits in the R

counter latch, ABP2 and ABP1, control the width of the pulse

(see Figure 25).

Data Sheet

HI

R DIVIDER

UP

D1

Q1

U1

CLR1

PROGRAMMABLE

U3

DELAY

ABP1

ABP2

HI

N DIVIDER

CLR2

DOWN

D2

Q2

U2

VP CHARGE

PUMP

CP

CPGND

R DIVIDER

N DIVIDER

CP OUTPUT

Figure 17. PFD Simplified Schematic and Timing (In Lock)

LOCK DETECT

The LD pin outputs a lock detect signal. Digital lock detect is

active high. When lock detect precision (LDP) in the R counter

latch is set to 0, digital lock detect is set high when the phase error

on three consecutive phase detector cycles is <15 ns.

When LDP is set to 1, five consecutive cycles of <15 ns phase

error are required to set the lock detect. It stays set high until a

phase error of >25 ns is detected on any subsequent PD cycle.

INPUT SHIFT REGISTER

The digital section of the ADF4360 family includes a 24-bit

input shift register, a 14-bit R counter, and an 18-bit N counter,

comprising a 5-bit A counter and a 13-bit B counter. Data is

clocked into the 24-bit shift register on each rising edge of CLK.

The data is clocked in MSB first. Data is transferred from the

shift register to one of four latches on the rising edge of LE. The

destination latch is determined by the state of the two control

bits (C2, C1) in the shift register. The two LSBs, DB1 and DB0,

are shown in Figure 2.

Rev. B | Page 10 of 24

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