ADC912A 데이터 시트보기 (PDF) - Analog Devices

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ADC912A

CMOS Microprocessor-Compatible 12-Bit A/D Converter

Analog Devices 

ADC912A

WAFER TEST LIMITS (@ VDD = +5 V, VSS = –12 V or –15 V, VREF = –5 V, AIN = 0 V to 10 V, and TA = 25؇C, unless otherwise noted.)

Parameter

Symbol Conditions

ADC912AG

Limit

Unit

Integral Nonlinearity

Differential Nonlinearity

Offset Error

Gain Error

Analog Input Resistance

Logic Input High Voltage

Logic Input Low Voltage

Logic Input Current

Logic Output High Voltage

Logic Output Low Voltage

Positive Supply Current

Negative Supply Current

INL

DNL

VZSE

GFSE

RAIN

VINH

VINL

IIN

VOH

VOL

IDD

ISS

±1

±1

Guaranteed by Design

±8

±8

4/6

CS, RD, HBEN

2.4

CS, RD, HBEN

0.8

CS, RD, HBEN

±1

ISOURCE = 0.2 mA

4

ISINK = 1.6 mA

0.4

VDD = +5 V, CS = RD = VDD, AIN = +10 V

7

VSS = –12 V, CS = RD = VDD, AIN = +10 V

5

LSB max

LSB max

LSB max

LSB max

kΩ min/max

V min

V max

µA max

V min

V max

mA max

mA max

NOTE

Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed

for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

10V

C1

–5V

C1

R

+

C2

R

C2

+

NC

R = 10⍀

C1 = 0.01␮F

C2 = 4.7␮F

NC = NO CONNECT

R

C1

1

24 R

2

23

C1

3

22 NC

4

21

R

5 ADC912A 20 R

6 TOP VIEW 19

(Not to Scale)

7

18 NC

R

8

17

9

16 NC

10

15 NC

11

14 NC

12

13 NC

POWER SUPPLY SEQUENCE:

+5V, –15V, –5V, +10V

+5V

+

C2

–15V

C2

+

Figure 9. Burn-In Circuit

REV. B

–5–

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