AD9943 데이터 시트보기 (PDF) - Analog Devices
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AD9943 Datasheet PDF : 20 Pages
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AD9943/AD9944
TIMING SPECIFICATIONS
CL = 20 pF, fSAMP = 25 MHz. See CCD-mode timing in Figure 14 and Figure 15, and serial timing in Figure 10 and Figure 11.
Table 5.
Parameter
SAMPLE CLOCKS
DATACLK, SHP, SHD Clock Period
DATACLK High/Low Pulse Width
SHP Pulse Width
SHD Pulse Width
CLPOB Pulse Width1
SHP Rising Edge to SHD Falling Edge
SHP Rising Edge to SHD Rising Edge
Internal Clock Delay
DATA OUTPUTS
Output Delay
Pipeline Delay
SERIAL INTERFACE
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
Symbol
tCONV
tADC
tSHP
tSHD
tCOB
tS1
tS2
tID
tOD
fSCLK
tLS
tLH
tDS
tDH
Min
Typ
Max
Unit
40
16
20
10
10
2
20
10
16
20
3.0
ns
ns
ns
ns
Pixels
ns
ns
ns
9.5
ns
9
Cycles
10
MHz
10
ns
10
ns
10
ns
10
ns
1 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Rev. B | Page 6 of 20
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