AD9851BRS(RevC) 데이터 시트보기 (PDF) - Analog Devices
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AD9851BRS Datasheet PDF : 23 Pages
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AD9851
W CLK #1
W CLK #1
FQ UD
FQ UD
MICROPROCESSOR
OR
MICROCONTROLLER
RESET
8-BIT DATA BUS
RESET
W CLK #2
W CLK #2
W CLK IOUT
AD9851
#1
FQ UD
RESET
REF
CLOCK
90
PHASE
DIFFERENCE
RESET IOUT
FQ UD
AD9851
#2
W CLK
Figure 7. Application Showing Synchronization of Two
AD9851 DDSs to Form a Quadrature Oscillator
After a common RESET command is issued, separate W_CLKs
allow independent programming of each AD9851 40-bit input
register via the 8-bit data bus or serial input pin. A common
FQ_UD pulse is issued after programming is completed to
simultaneously engage both oscillators at their specified fre-
quency and phase.
AD9851
؋6
IOUT
BANDPASS
FILTER
AMPLIFIER
50⍀
50⍀
240MHz
30MHz
AD9851
CLOCK SPECTRUM
FUNDAMENTAL
FC – FO
IMAGE
FC + FO
IMAGE
FCLK
FINAL OUTPUT
SPECTRUM
FC + FO
IMAGE
BANDPASS
FILTER
60 120 180 240
FREQUENCY – MHz
240
FREQUENCY – MHz
Figure 8. Deriving a High Frequency Output Signal from
the AD9851 by Using an “Alias” or Image Signal
Differential DAC output connection (Figure 9) for reduction of
common-mode signals and to allow highly reactive filters to be
driven without a filter input termination resistor (see above
single-ended example, Figure 8). A 6 dB power advantage is
obtained at the filter output as compared with the single-ended
example, since the filter need not be doubly terminated.
REFERENCE
CLOCK
DIFFERENTIAL
TRANSFORMER-COUPLED
21
OUTPUT
FILTER
AD9851
DDS
20
50⍀
1:1 TRANSFORMER
i.e., MINI-CIRCUITS T1–1T
50⍀
Figure 9. Differential DAC Output Connection for Reduc-
tion of Common-Mode Signals
The AD9851 RSET input being driven by an external DAC
(Figure 10) to provide amplitude modulation or fixed, digital
amplitude control of the DAC output current. Full description
of this application is found as a “Technical Note” on the AD9851
web page (site address is www.analog.com) under “Related
Information.” An Analog Devices application note for the
AD9850, AN-423, describes another method of amplitude
control using an enhancement-mode MOSFET that is equally
applicable to the AD9851.
NOTE: If the 6× REFCLK Multiplier of the AD9851 is en-
gaged, the 125 MHz clocking source shown in Figure 10 can be
reduced by a factor of six.
DATA
GENERATOR 10 BITS
e.g., DG-2020
+5V
10-BIT DAC
AD9731
–5V
+5V
+5V
DIFFERENTIAL
20mA
MAX
330⍀ 4k⍀ 12
RSET
TRANSFORMER-COUPLED
IOUT 21
OUTPUT
200⍀
50⍀
AD9851
125MHz
DDS
9
IOUT 20
CONTROL
DATA
50⍀
1:1 TRANSFORMER
COMPUTER
Figure 10. The AD9851 RSET Input Being Driven by an External DAC
REV. C
–7–
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