AD9626-250EBZ 데이터 시트보기 (PDF) - Analog Devices
부품명
상세내역
일치하는 목록
AD9626-250EBZ Datasheet PDF : 36 Pages
| |||
AD9626
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
Table 3.
Parameter1
CLOCK INPUTS
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Temp
Full
Full
Full
Full
Input Common-Mode Range Full
High Level Input Voltage (VIH) Full
Low Level Input Voltage (VIL) Full
Input Resistance (Differential) Full
Input Capacitance
Full
LOGIC INPUTS
Logic 1 Voltage
Full
Logic 0 Voltage
Full
Logic 1 Input Current (SDIO) Full
Logic 0 Input Current (SDIO) Full
Logic 1 Input Current
Full
(SCLK, PDWN, CSB, RESET)
Logic 0 Input Current
Full
(SCLK, PDWN, CSB, RESET)
Input Capacitance
25°C
LOGIC OUTPUTS2
High Level Output Voltage Full
Low Level Output Voltage
Full
Output Coding
AD9626-170
Min
Typ Max
AD9626-210
Min
Typ Max
AD9626-250
Min
Typ Max
CMOS/LVDS/LVPECL
1.2
0.2
6
AVDD −
0.3
AVDD +
1.6
1.1
AVDD
1.2
3.6
0
0.8
16
20 24
4
CMOS/LVDS/LVPECL
1.2
0.2
6
AVDD −
0.3
AVDD +
1.6
1.1
AVDD
1.2
3.6
0
0.8
16
20 24
4
CMOS/LVDS/LVPECL
1.2
0.2
6
AVDD −
0.3
AVDD +
1.6
1.1
AVDD
1.2
3.6
0
0.8
16
20 24
4
0.8 ×
AVDD
0.2 ×
AVDD
0
−60
55
0
4
0.8 ×
AVDD
0.8 ×
AVDD
0.2 ×
AVDD
0
−60
55
0
4
0.2 ×
AVDD
0
−60
50
0
4
DRVDD − 0.05
DRVDD − 0.05
DRVDD − 0.05
GND + 0.05
GND + 0.05
GND + 0.05
Twos complement, Gray code, or offset binary (default)
Unit
V
V p-p
V
V
V
V
kΩ
pF
V
V
μA
μA
μA
μA
pF
V
V
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2 LVDS RTERMINATION = 100 Ω.
Rev. 0 | Page 5 of 36
Share Link: 