AD9220ARS(1998) 데이터 시트보기 (PDF) - Analog Devices
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AD9220ARS Datasheet PDF : 28 Pages
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AD9221/AD9223/AD9220
INTRODUCTION
The AD9221/AD9223/AD9220 are members of a high perfor-
mance, complete single-supply 12-bit ADC product family based
on the same CMOS pipelined architecture. The product family
allows the system designer an upward or downward component
selection path based on dynamic performance, sample rate, and
power. The analog input range of the AD9221/AD9223/AD9220
is highly flexible allowing for both single-ended or differential
inputs of varying amplitudes which can be ac or dc coupled.
Each device shares the same interface options, pinout and pack-
age offering.
The AD9221/AD9223/AD9220 utilize a four-stage pipeline
architecture with a wideband input sample-and-hold amplifier
(SHA) implemented on a cost-effective CMOS process. Each
stage of the pipeline, excluding the last stage, consists of a low
resolution flash A/D connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
amplifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each of the stages to facilitate digital
correction of flash errors. The last stage simply consists of a
flash A/D.
The pipeline architecture allows a greater throughput rate at the
expense of pipeline delay or latency. This means that while the
converter is capable of capturing a new input sample every clock
cycle, it actually takes three clock cycles for the conversion to be
fully processed and appear at the output. This latency is not a
concern in most applications. The digital output, together with
the out-of-range indicator (OTR), is latched into an output
buffer to drive the output pins. The output drivers of the AD9220,
AD9221 and AD9223 can be configured to interface with +5 V
or +3.3 V logic families.
The AD9221/AD9223/AD9220 use both edges of the clock in
their internal timing circuitry (see Figure 1 and specification
page for exact timing requirements). The A/D samples the ana-
log input on the rising edge of the clock input. During the clock
low time (between the falling edge and rising edge of the clock),
the input SHA is in the sample mode; during the clock high
time it is in hold. System disturbances just prior to the rising
edge of the clock and/or excessive clock jitter may cause the
input SHA to acquire the wrong value, and should be minimized.
The internal circuitry of both the input SHA and individual
pipeline stages of each member of the product family are opti-
mized for both power dissipation and performance. An inherent
tradeoff exists between the input SHA’s dynamic performance
and its power dissipation. Figures 29 and 30 shows this tradeoff
by comparing the full-power bandwidth and settling time of the
AD9221/AD9223/AD9220. Both figures reveal that higher
full-power bandwidths and faster settling times are achieved at
the expense of an increase in power dissipation. Similarly, a
tradeoff exists between the sampling rate and the power dissipated
in each stage.
As previously stated, the AD9220, AD9221 and AD9223 are
similar in most aspects except for the specified sampling rate,
power consumption, and dynamic performance. The product
family is highly flexible providing several different input ranges
and interface options. As a result, many of the application issues
and tradeoffs associated with these resulting configurations are
also similar. The data sheet is structured such that the designer
can make an informed decision in selecting the proper A/D and
optimizing its performance to fit the specific application.
0
AD9220
–3
AD9223
–6
AD9221
–9
–12
1
10
100
FREQUENCY – MHz
Figure 29. Full-Power Bandwidth
4000
AD9220
3000
AD9223
AD9221
2000
1000
0
0
10
20
30
40
50
60
SETTLING TIME – ns
Figure 30. Settling Time
ANALOG INPUT AND REFERENCE OVERVIEW
Figure 31, a simplified model of the AD9221/AD9223/AD9220,
highlights the relationship between the analog inputs, VINA,
VINB, and the reference voltage, VREF. Like the voltage
applied to the top of the resistor ladder in a flash A/D converter,
the value VREF defines the maximum input voltage to the A/D
core. The minimum input voltage to the A/D core is automatically
defined to be –VREF.
VINA
AD9221/23/20
+VREF
VCORE
A/D
12
CORE
VINB
–VREF
Figure 31. AD9221/AD9223/AD9220 Equivalent Functional
Input Circuit
REV. B
–9–
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