AD8159 데이터 시트보기 (PDF) - Analog Devices

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AD8159

3.2 Gbps Quad Buffer Mux/Demux

Analog Devices 

TEST CIRCUITS

All graphs were generated using the setup shown in Figure 32, unless otherwise specified.

TERADYNE FR4 TEST BACKPLANE

GBX4 TO SMA DAUGHTER CARDS

AD8159

DIFFERENTIAL STRIPLINE TRACES

8mm WIDE, 8mm SPACE, 8mm HEIGHT

TRACE LENGTHS = 6", 18", 24", 30" + 3" × 2 DAUGHTER CARDS

Figure 31. Test Backplane

0.25"

DATA OUT

50Ω CABLE

PATTERN

GENERATOR

NOTES

1. SINGLE-ENDED REPRESENTATION

A

C

B

AD8159

AC-COUPLED

A

EVALUATION BOARD

C

B

50Ω CABLE

50Ω

50Ω

TEST BACKPLANE

Figure 32. AC-Coupled Test Circuit

50Ω CABLE

HIGH SPEED

REAL-TIME

OSCILLOSCOPE

50Ω

DATA OUT

50Ω CABLE

PATTERN

GENERATOR

NOTES

1. SINGLE-ENDED REPRESENTATION

A

C

B

AD8159

DC-COUPLED

A

EVALUATION BOARD

C

B

50Ω CABLE

50Ω

50Ω

TEST BACKPLANE

Figure 33. DC-Coupled Test Circuit

Note: Test Circuit Used for Figure 28

50Ω CABLE

HIGH SPEED

REAL-TIME

OSCILLOSCOPE

50Ω

Rev. A | Page 13 of 24

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