AD7980(RevC) 데이터 시트보기 (PDF) - Analog Devices
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AD7980 Datasheet PDF : 28 Pages
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Data Sheet
AD7980
TIMING SPECIFICATIONS
−40°C to +125°C, VDD = 2.37 V to 2.63 V, VIO = 3.3 V to 5.5 V, unless otherwise stated. See Figure 2 and Figure 3 for load conditions.
Table 4.
Parameter
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Period (Chain Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO Above 3 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (Chain Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
Symbol Min Typ Max Unit
tCONV
500
710 ns
tACQ
290
ns
tCYC
1000
ns
tCNVH
10
ns
tSCK
ns
10.5
ns
12
ns
13
ns
15
ns
tSCK
ns
11.5
ns
13
ns
14
ns
16
ns
tSCKL
4.5
ns
tSCKH
4.5
ns
tHSDO
3
ns
tDSDO
9.5
ns
11
ns
12
ns
14
ns
tEN
10
ns
15
ns
tDIS
20
ns
tSSDICNV
5
ns
tHSDICNV
2
ns
tHSDICNV
0
ns
tSSCKCNV
5
ns
tHSCKCNV
5
ns
tSSDISCK
2
ns
tHSDISCK
3
ns
tDSDOSDI
15
ns
500µA IOL
TO SDO
CL
20pF
500µA IOH
1.4V
Figure 2. Load Circuit for Digital Interface Timing
X% VIO1
tDELAY
VIH2
VIL2
Y% VIO1
tDELAY
VIH2
VIL2
1FOR VIO ≤ 3.0V, X = 90 AND Y = 10; FOR VIO > 3.0V X = 70, AND Y = 30.
2MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS
SPECIFICATIONS IN TABLE 3.
Figure 3. Voltage Levels for Timing
Rev. C | Page 5 of 28
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