AD7821 데이터 시트보기 (PDF) - Analog Devices
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AD7821 Datasheet PDF : 16 Pages
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AD7821
TIMING CHARACTERISTICS1 (VDD = +5 V ؎ 5%, VSS = 0 V or –5 V ؎ 5%; Unipolar or Bipolar Input Range)
Parameter
Limit at +25؇C
(All Versions)
Limit at
TMIN, TMAX
(K, B Versions)
Limit at
TMIN, TMAX
(T Version)
Unit
Conditions/Comments
tCSS
tCSH
tRDY2
tCRD
tACC03
tINTH2
tDH4
tP
tWR
tRD
tREAD1
tACC13
tRI
tINTL2
tREAD2
tACC23
tIHWR2
tID3
0
0
70
700
tCRD + 25
tCRD + 50
50
80
15
60
350
250
10
250
160
160
185
150
380
500
65
65
90
80
30
45
0
0
85
875
tCRD + 30
tCRD + 65
–
85
15
70
425
325
10
350
205
205
235
185
–
610
75
75
110
100
35
60
0
0
100
975
tCRD + 35
tCRD + 75
–
90
15
80
500
400
10
450
240
240
275
220
–
700
85
85
130
120
40
70
ns min
ns min
ns max
ns max
ns max
ns max
ns typ
ns max
ns min
ns max
ns min
ns min
µs max
ns min
ns min
ns max
ns max
ns max
ns typ
ns max
ns min
ns max
ns max
ns max
ns max
ns max
CS to RD/WR Setup Time
CS to RD/WR Hold Time
CS to RDY Delay. Pull-Up
Resistor 5 kΩ
Conversion Time (RD Mode)
Data Access Time (RD Mode)
CL = 20 pF
CL = 100 pF
RD to INT Delay (RD Mode)
Data Hold Time
Delay Time Between Conversions
Write Pulsewidth
Delay Time between WR and RD Pulses
RD Pulsewidth (WR-RD Mode, see Figure 12b)
Determined by tACC1
Data Access Time (WR-RD Mode, see Figure 12b)
CL = 20 pF
CL = 100 pF
RD to INT Delay
WR to INT Delay
RD Pulsewidth (WR-RD Mode, see Figure 12a)
Determined by tACC2
Data Access Time (WR-RD Mode, see Figure 12a)
CL = 20 pF
CL = 100 pF
WR to INT Delay (Stand-Alone Operation)
Data Access Time after INT
(Stand-Alone Operation)
CL = 20 pF
CL = 100 pF
NOTES
1Sample tested at +25°C to ensure compliance. All input control signals are specified with tRISE = tFALL = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
2CL = 50 pF.
3Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
Test Circuits
a. High Z to VOH
b. High Z to VOL
Figure 1. Load Circuits for Data Access Time Test
ORDERING GUIDE
Model1
Temperature
Range
Total
Unadjusted Package
Error (LSB) Option2
AD7821KN
AD7821KP
AD7821KR
AD7821BQ
AD7821TQ
AD7821TE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–55°C to +125°C
± 1 max
± 1 max
± 1 max
± 1 max
± 1 max
± 1 max
N-20
P-20A
RW-20
Q-20
Q-20
E-20A
NOTES
1To order MIL-STD-883, Class B processed parts, add /883B to part
number. Contact local sales office for military data sheet.
2E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded
Chip Carrier; Q = Cerdip; R = SOIC.
a. VOH to High Z
b. VOL to High Z
Figure 2. Load Circuits for Data Hold Time Test
REV. B
–3–
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