AD7699BCPZRL7 데이터 시트보기 (PDF) - Analog Devices
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AD7699BCPZRL7 Datasheet PDF : 28 Pages
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AD7699
TIMING SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VREF = 4.096 to VDD, VIO = 1.8 V to VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width
Data Write/Read During Conversion
SCK Period
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
VIO Above 1.8 V
CNV Low to SDO D15 MSB Valid
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
VIO Above 1.8 V
CNV High or Last SCK Falling Edge to SDO High Impedance
CNV Low to SCK Rising Edge
DIN Valid Setup Time from SCK Falling Edge
DIN Valid Hold Time from SCK Falling Edge
Symbol
tCONV
tACQ
tCYC
tCNVH
tDATA
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
tDIS
tCLSCK
tSDIN
tHDIN
Min
Typ
400
2
10
tDSDO + 2
11
11
4
10
5
5
Max
1.6
1.2
16
17
18
21
28
15
17
18
22
25
32
Unit
µs
ns
µs
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1 See Figure 2 and Figure 3 for load conditions.
500µA IOL
TO SDO
CL
50pF
1.4V
500µA IOH
Figure 2. Load Circuit for Digital Interface Timing
30% VIO
tDELAY
70% VIO
2V OR VIO – 0.5V1
0.8V OR 0.5V2
tDELAY
2V OR VIO – 0.5V1
0.8V OR 0.5V2
1 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
2 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
Figure 3. Voltage Levels for Timing
Rev. 0 | Page 5 of 28
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