AD7694(Rev0) 데이터 시트보기 (PDF) - Analog Devices

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AD7694
(Rev.:Rev0)

16-Bit, 250 kSPS PulSAR ADC in MSOP

Analog Devices 

AD7694

APPLICATION INFORMATION

IN+

REF

GND

MSB

SWITCHES CONTROL

LSB SW+

32,768C 16,384C

4C

2C

C

C

32,768C 16,384C

4C

2C

C

C

COMP

CONTROL

LOGIC

BUSY

OUTPUT CODE

MSB

LSB SW–

CNV

IN–

Figure 18. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD7694 is a low power, single-supply, 16-bit ADC using a

successive approximation architecture. It is capable of con-

verting 250,000 samples per second (250 kSPS) and powers

down between conversions. When operating at 100 SPS, for

example, it consumes typically 4 µW, ideal for battery-powered

applications.

The AD7694 provides the user with on-chip track-and-hold and

does not exhibit any pipeline delay or latency, making it ideal

for multiple, multiplexed channel applications.

toggles these switches, starting with the MSB, in order to bring

the comparator back into a balanced condition. After the

completion of this process, the part returns to the acquisition

phase and the control logic generates the ADC output code.

Because the AD7694 has an on-board conversion clock, the

serial clock, SCK, is not required for the conversion process.

TRANSFER FUNCTIONS

The ideal transfer function for the AD7694 is shown in

Figure 19 and Table 8.

The AD7694 is specified from 2.7 V to 5.25 V. It is housed in a

8-lead MSOP. The AD7694 is an improved second source to

LTC1864 and LTC1864L. For even better performance, the

AD7685 should be considered.

111...111

111...110

111...101

CONVERTER OPERATION

The AD7694 is a successive approximation ADC based on a

charge redistribution DAC. Figure 18 shows the simplified

schematic of the ADC. The capacitive DAC consists of two

identical arrays of 16 binary weighted capacitors, which are

connected to the two comparator inputs.

During the acquisition phase, terminals of the array tied to the

comparator’s input are connected to GND via SW+ and SW−.

All independent switches are connected to the analog inputs.

Thus, the capacitor arrays are used as sampling capacitors and

acquire the analog signal on the IN+ and IN− inputs. When the

acquisition phase is complete and the CNV input goes high, a

conversion phase begins. When the conversion phase begins,

SW+ and SW− are opened first. The two capacitor arrays are

then disconnected from the inputs and connected to the GND

input. Thus, the differential voltage between the inputs, IN+ and

IN−, captured at the end of the acquisition phase applies to the

comparator inputs, causing the comparator to become unbal-

anced. By switching each element of the capacitor array between

GND and REF, the comparator input varies by binary weighted

voltage steps (VREF/2, VREF/4...VREF/65536). The control logic

000...010

000...001

000...000

–FS

–FS + 1 LSB

–FS + 0.5 LSB

+FS – 1 LSB

+FS – 1.5 LSB

ANALOG INPUT

Figure 19. ADC Ideal Transfer Function

Table 8. Output Codes and Ideal Input Voltages

Description

FSR – 1 LSB

Midscale + 1 LSB

Midscale

Midscale – 1 LSB

–FSR + 1 LSB

–FSR

Analog Input

VREF = 5 V

4.999924 V

2.500076 V

2.5 V

2.499924 V

76.3 µV

0V

Digital Output Code

Hexadecimal

FFFF2

8001

8000

7FFF

0001

00003

2 This is also the code for an overranged analog input (VIN+ – VIN– above

VREF – VGND).

3 This is also the code for an underranged analog input (VIN+ – VIN– below VGND).

Rev. 0 | Page 12 of 16

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