AD7451_02 데이터 시트보기 (PDF) - Analog Devices
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AD7451_02 Datasheet PDF : 15 Pages
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PRELIMINARY TECHNICAL DATA
AD7451/AD7441
MODES OF OPERATION
The mode of operation of the AD7451 and the AD7441 is
selected by controlling the logic state of the CS signal during
a conversion. There are two possible modes of operation,
Normal Mode and Power-Down Mode. The point at which
CS is pulled high after the conversion has been initiated will
determine whether or not the AD7451/41 will enter the
power-down mode. Similarly, if already in power-down, CS
controls whether the devices will return to normal operation
or remain in power-down. These modes of operation are
designed to provide flexible power management options.
These options can be chosen to optimize the power dissipa-
tion/throughput rate ratio for differing application
requirements.
Normal Mode
This mode is intended for fastest throughput rate perfor-
mance. The user does not have to worry about any
power-up times with the AD7451/41 remaining fully
powered up all the time. Figure 5 shows the general dia-
gram of the operation of the AD7451/41 in this mode.
The conversion is initiated on the falling edge of CS as
described in the ‘Serial Interface Section’. To ensure the
part remains fully powered up, CS must remain low until
at least 10 SCLK falling edges have elapsed after the fall-
ing edge of CS.
If CS is brought high any time after the 10th SCLK fall-
ing edge, but before the 16th SCLK falling edge, the part
will remain powered up but the conversion will be termi-
nated and SDATA will go back into three-state. Sixteen
serial clock cycles are required to complete the conversion
and access the complete conversion result. CS may idle
high until the next conversion or may idle low until some-
time prior to the next conversion. Once a data transfer is
complete, i.e. when SDATA has returned to three-state,
another conversion can be initiated after the quiet time,
tQUIET has elapsed by again bringing CS low.
Once CS has been brought high in this window of
SCLKs, the part will enter power down and the conver-
sion that was initiated by the falling edge of CS will be
terminated and SDATA will go back into three-state.
The time from the rising edge of CS to SDATA three-
state enabled will never be greater than t8 (see the
‘Timing Specifications’). If CS is brought high before
the second SCLK falling edge, the part will remain in
normal mode and will not power-down. This will avoid
accidental power-down due to glitches on the CS line.
In order to exit this mode of operation and power the
AD7451/41 up again, a dummy conversion is performed.
On the falling edge of CS the device will begin to power
up, and will continue to power up as long as CS is held
low until after the falling edge of the 10th SCLK. The
device will be fully powered up after 1µsec has elapsed
and, as shown in Figure 7, valid data will result from the
next conversion.
If CS is brought high before the 10th falling edge of
SCLK, the AD7451/41 will again go back into power-
down. This avoids accidental power-up due to glitches on
the CS line or an inadvertent burst of eight SCLK cycles
while CS is low. So although the device may begin to
power up on the falling edge of CS, it will again power-
down on the rising edge of CS as long as it occurs before
the 10th SCLK falling edge.
+5
12
10
SCLK
SDATA
THREE STATE
+5
Figure 6. Entering Power Down Mode
1
SCLK
Power up Time
10
16
The power up time of the AD7451/41 is typically 1µsec,
which means that with any frequency of SCLK up to
18MHz, one dummy cycle will always be sufficient to
SDATA
4 LEADING ZEROS + CONVERSION RESULT
Figure 5. Normal Mode Operation
Power Down Mode
This mode is intended for use in applications where
slower throughput rates are required; either the ADC is
powered down between each conversion, or a series of
conversions may be performed at a high throughput rate
and the ADC is then powered down for a relatively long
duration between these bursts of several conversions.
When the AD7451/AD7441 is in the power down mode,
all analog circuitry is powered down. To enter power
down mode, the conversion process must be interrupted
by bringing CS high anywhere after the second falling
edge of SCLK and before the tenth falling edge of SCLK
as shown in Figure 6.
allow the device to power-up. Once the dummy cycle is
complete, the ADC will be fully powered up and the input
signal will be acquired properly. The quiet time tQUIET
must still be allowed from the point at which the bus goes
back into three-state after the dummy conversion, to the
next falling edge of CS.
When running at the maximum throughput rate of
1MSPS, the AD7451/41 will power up and acquire a sig-
nal within ±0.5LSB in one dummy cycle, i.e. 1µs. When
powering up from the power-down mode with a dummy
cycle, as in Figure 7, the track and hold, which was in
hold mode while the part was powered down, returns to
track mode after the first SCLK edge the part receives
after the falling edge of CS. This is shown as point A in
Figure 7.
–14–
REV. PrC
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