AD7451BRM 데이터 시트보기 (PDF) - Analog Devices
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AD7451BRM Datasheet PDF : 15 Pages
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PRELIMINARY TECHNICAL DATA
AD7451/AD7441
SERIAL INTERFACE
Figures 1 and 2 show detailed timing diagrams for the
serial interface of the AD7451 and the AD7441 respec-
tively. The serial clock provides the conversion clock and
also controls the transfer of data from the device during
conversion. CS initiates the conversion process and frames
the data transfer. The falling edge of CS puts the track
and hold into hold mode and takes the bus out of three-
state. The analog input is sampled and the conversion
initiated at this point. The conversion will require 16
SCLK cycles to complete.
Once 13 SCLK falling edges have occurred, the track and
hold will go back into track on the next SCLK rising edge
as shown at point B in Figures 1 and 2. On the 16th
SCLK falling edge the SDATA line will go back into
three-state.
If the rising edge of CS occurs before 16 SCLKs have
elapsed, the conversion will be terminated and the SDATA
line will go back into three-state on the 16th SCLK falling
edge.
The conversion result from the AD7451/41 is provided on
the SDATA output as a serial data streatm. The bits are
clocked out on the falling edge of the SCLK input. The data
streatm of the AD7451 consists of four leading zeros,
followed by 12 bits of conversion data which is provided MSB
first; the data stream of the AD7441 consists of four leading
zeros, followed by the 10 bits of conversion data, followed by
two trailing zeros, which is also provided MSB first. In both
cases, the output coding is straight (natural) binary.
16 serial clock cycles are required to perform a conversion
and to access data from the AD7451/41. CS going low
provides the first leading zero to be read in by the micro-
controller or DSP. The remaining data is then clocked out
on the subsequent SCLK falling edges beginning with the
second leading zero. Thus the first falling clock edge on the
serial clock provides the second leading zero. The final bit
in the data transfer is valid on the 16th falling edge, having
been clocked out on the previous (15th) falling edge. Once
the conversion is complete and the data has been accessed
after the 16 clock cycles, it is important to ensure that, before
the next conversion is initiated, enough time is left to meet
the acquisition and quiet time specifications - see the Timing
Examples. To achieve 1MSPS with an 18MHz clock for
+5
VDD = 3 V and 5 V, an 18 clock burst will perform the
conversion and leave enough time before the next conversion
for the acquisition and quiet time.
In applications with a slower SCLK, it may be possible to
read in data on each SCLK rising edge i.e. the first rising
edge of SCLK after the CS falling edge would have the
leading zero provided and the 15th SCLK edge would have
DB0 provided.
Timing Example 1
Having FSCLK = 18MHz and a throughput rate of
1MSPS gives a cycle time of:
1/Throughput = 1/1000000 = 1µs
A cycle consists of:
t2 + 12.5 (1/FSCLK) + tACQ = 1µs.
Therefore if t2 = 10ns then:
10ns + 12.5(1/18MHz) + tACQ = 1µs
tACQ = 296ns
This 296ns satisfies the requirement of 200ns for tACQ.
From Figure 4, tACQ comprises of:
2.5(1/FSCLK) + t8 + tQUIET
where t8 = 35ns. This allows a value of 122ns for tQUIET
satisfying the minimum requirement of 25ns.
Timing Example 2
Having FSCLK = 5MHz and a throughput rate of
315kSPS gives a cycle time of :
1/Throughput = 1/315000 = 3.174µs
A cycle consists of:
t2 + 12.5 (1/FSCLK) + tACQ = 3.174µs.
Therefore if t2 is 10ns then:
10ns + 12.5(1/5MHz) + tACQ = 3.174µs
tACQ = 664ns
This 664ns satisfies the requirement of 200ns for tACQ.
From Figure 4, tACQ comprises of:
2.5(1/FSCLK) + t8 + tQUIET
where t8 = 35ns. This allows a value of 129ns for tQUIET
satisfying the minimum requirement of 25ns.
As in this example and with other slower clock values, the
signal may already be acquired before the conversion is
complete but it is still necessary to leave 25ns minimum
tQUIET between conversions. In example 2 the signal should
be fully acquired at approximately point C in Figure 4.
t CONVERT
SCLK
10ns t2
t5
1
2
3
4
5
B
C
13
14
15
16
t6
t8
tQ U IE T
12.5(1/fSCLK )
t ACQUISITION
REV. PrC
1/Throughput
Figure 4. Serial Interface Timing Example
–13–
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