EVAL-AD7490CB(RevA) 데이터 시트보기 (PDF) - Analog Devices

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EVAL-AD7490CB
(Rev.:RevA)

16-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOP

Analog Devices 

1.0

0.8

VDD ؍VDRIVE ؍5V

TEMP ؍25 C

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

0

512 1024 1536 2048 2560 3072 3584 4096

CODE

TPC 6. Typical INL

AD7490

1.0

0.8

VDD ؍VDRIVE ؍5V

TEMP ؍25 C

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

0

512 1024 1536 2048 2560 3072 3584 4096

CODE

TPC 7. Typical DNL

CONTROL REGISTER

The Control Register on the AD7490 is a 12-bit, write-only register. Data is loaded from the DIN pin of the AD7490 on the falling

edge of SCLK. The data is transferred on the DIN line at the same time as the conversion result is read from the part. The data transferred

on the DIN line corresponds to the AD7490 configuration for the next conversion. This requires 16 serial clocks for every data transfer.

Only the information provided on the first 12 falling clock edges (after CS falling edge) is loaded to the Control Register. MSB denotes

the first bit in the data stream. The bit functions are outlined in Table I.

MSB

WRITE

SEQ

ADD3

Table I. Control Register Bit Functions

LSB

ADD2

ADD1

ADD0

PM1

PM0 SHADOW WEAK/TRI RANGE CODING

Bit Name

Description

11

WRITE

The value written to this bit of the Control Register determines whether the following 11 bits will be loaded

to the Control Register or not. If this bit is a 1, the following 11 bits will be written to the Control Register;

if it is a 0, the remaining 11 bits are not loaded to the Control Register and so it remains unchanged.

10

SEQ

The SEQ Bit in the Control Register is used in conjunction with the Shadow Bit to control the use of the

sequencer function and access the Shadow Register. (See Table IV.)

9–6 ADD3–ADD0 These four address bits are loaded at the end of the present conversion sequence, and select which analog

input channel is to be converted on in the next serial transfer, or may select the final channel in a con-

secutive sequence as described in Table IV. The selected input channel is decoded as shown in Table II.

The address bits corresponding to the conversion result are also output on DOUT prior to the 12 bits of

data (see Serial Interface section). The next channel to be converted on will be selected by the mux on

the 14th SCLK falling edge.

5, 4 PM1, PM0

Power Management Bits. These two bits decode the mode of operation of the AD7490 as shown in Table III.

3

SHADOW

The Shadow Bit in the Control Register is used in conjunction with the SEQ Bit to control the use of the

sequencer function and access the Shadow Register. (See Table IV.)

2

WEAK/TRI

This bit selects the state of the DOUT line at the end of the current serial transfer. If it is set to 1, the

DOUT line will be weakly driven to the channel address bit ADD3 of the ensuing conversion. If this bit is

set to 0, then DOUT will return to three-state at the end of the serial transfer. See the Serial Interface

section for more details.

1

RANGE

This bit selects the analog input range to be used on the AD7490. If it is set to 0, then the analog input range

will extend from 0 V to 2 ϫ REFIN. If it is set to 1, then the analog input range will extend from 0 V to

REFIN (for the next conversion). For 0 V to 2 ϫ REFIN, VDD = 4.75 V to 5.25 V.

0

CODING

This bit selects the type of output coding the AD7490 will use for the conversion result. If this bit is set to 0,

the output coding for the part will be twos complement. If this bit is set to 1, the output coding from the

part will be straight binary (for the next conversion).

REV. A

–9–

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