AD7490(RevA) 데이터 시트보기 (PDF) - Analog Devices
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AD7490 Datasheet PDF : 24 Pages
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AD7490
AD7490 to ADSP-21xx
The ADSP-21xx family of DSPs are interfaced directly to the
AD7490 without any glue logic required. The VDRIVE Pin of the
AD7490 takes the same supply voltage as that of the ADSP-218x.
This allows the ADC to operate at a higher voltage than the
serial interface, i.e., ADSP-218x, if necessary.
The SPORT0 Control Register should be set up as follows:
TFSW ϭ
INVRFS ϭ
DTYPE ϭ
SLEN ϭ
ISCLK ϭ
TFSR ϭ
IRFS ϭ
ITFS ϭ
RFSW ϭ 1, Alternate Framing
INVTFS ϭ 1, Active Low Frame Signal
00, Right Justify Data
1111, 16-Bit Datawords
1, Internal Serial Clock
RFSR ϭ 1, Frame Every Word
0
1
The connection diagram is shown in Figure 21. The ADSP-218x
has the TFS and RFS of the SPORT tied together, with TFS set
as an output and RFS set as an input. The DSP operates in
Alternate Framing Mode and the SPORT Control Register is set
up as described. The frame synchronization signal generated on the
TFS is tied to CS, and as with all signal processing applications,
equidistant sampling is necessary. However in this example, the
timer interrupt is used to control the sampling rate of the ADC and
under certain conditions, equidistant sampling may not be achieved.
The Timer Register for example is loaded with a value that will
provide an interrupt at the required sample interval. When an
interrupt is received, a value is transmitted with TFS/DT (ADC
control word). The TFS is used to control the RFS and thus the
reading of data. The frequency of the serial clock is set in the
SCLKDIV Register. When the instruction to transmit with TFS is
given, (i.e., AX0 ϭ TX0), the state of the SCLK is checked.
The DSP will wait until the SCLK has gone high, low and high
before transmission will start. If the timer and SCLK values are
chosen such that the instruction to transmit occurs on or near
the rising edge of SCLK, then the data may be transmitted or it
may wait until the next clock edge.
For example, if the ADSP-2189 with a 20 MHz crystal has an
overall master clock frequency of 40 MHz, then the master cycle
time would be 25 ns. If the SCLKDIV Register is loaded with the
value 3, a SCLK of 5 MHz is obtained, and eight master clock
periods will elapse for every 1 SCLK period. Depending on the
throughput rate selected, if the timer registers are loaded with
the value 803, 100.5 SCLKs will occur between interrupts and
subsequently between transmit instructions. This situation will
result in nonequidistant sampling as the transmit instruction is
occurring on a SCLK edge. If the number of SCLKs between
interrupts is a figure of N, then equidistant sampling will be
implemented by the DSP.
AD7490
SCLK
DOUT
CS
VDRIVE DIN
ADSP-218x*
SCLK
DR
RFS
TFS
DT
*ADDITIONAL PINS REMOVED FOR CLARITY
VDD
Figure 21. Interfacing to the ADSP-218x
AD7490 to DSP563xx
The connection diagram in Figure 22 shows how the AD7490 can
be connected to the ESSI (Synchronous Serial Interface) of the
DSP563xx family of DSPs from Motorola. Each ESSI (2 on board)
is operated in Synchronous Mode (SYN bit in CRB ϭ 1) with
internally generated 1-bit clock period frame sync for both Tx
and Rx (bits FSL1 ϭ 0 and FSL0 ϭ 0 in CRB). Normal operation
of the ESSI is selected by making MOD ϭ 0 in the CRB. Set
the word length to 16 by setting bits WL1 ϭ 1 and WL0 ϭ 0 in
CRA. The FSP Bit in the CRB should be set to 1 so the frame
sync is negative. It should be noted that for signal processing
applications, it is imperative that the frame synchronization
signal from the DSP563xx will provide equidistant sampling.
AD7490
SCLK
DOUT
CS
VDRIVE DIN
DSP563xx*
SCK
SRD
STD
SC2
*ADDITIONAL PINS REMOVED FOR CLARITY
VDD
Figure 22. Interfacing to the DSP563xx
In the example shown in Figure 22, the serial clock is taken from
the ESSI so the SCK0 Pin must be set as an output, SCKD ϭ 1.
The VDRIVE Pin of the AD7490 takes the same supply voltage as
that of the DSP563xx. This allows the ADC to operate at a higher
voltage than the serial interface, i.e., DSP563xx, if necessary.
REV. A
–19–
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