AD7401AYRWZ-RL 데이터 시트보기 (PDF) - Analog Devices

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AD7401AYRWZ-RL

Isolated Sigma-Delta Modulator

Analog Devices 

AD7401A

TIMING SPECIFICATIONS

VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, TA = −40°C to +125°C, unless otherwise noted.

Table 2.

Parameter1

fMCLKIN2, 3

t1 4

t24

t3

t4

Limit at TMIN, TMAX

20

5

25

15

0.4 × tMCLKIN

0.4 × tMCLKIN

Unit

MHz max

MHz min

ns max

ns min

ns min

ns min

Description

Master clock input frequency

Master clock input frequency

Data access time after MCLKIN rising edge

Data hold time after MCLKIN rising edge

Master clock low time

Master clock high time

1 Sample tested during initial release to ensure compliance.

2 Mark space ratio for clock input is 40/60 to 60/40 for fMCLKIN ≤ 16 MHz and 48/52 to 52/48 for 16 MHz < fMCLKIN < 20 MHz.

3 VDD1 = VDD2 = 5 V ± 5% for fMCLKIN > 16 MHz to 20 MHz.

4 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.

200µA

IOL

TO OUTPUT

PIN CL

25pF

1.6V

200µA

IOH

Figure 2. Load Circuit for Digital Output Timing Specifications

MCLKIN

MDAT

t4

t1

t2

t3

Figure 3. Data Timing

Rev. 0 | Page 5 of 20

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