AD73460(Rev0) 데이터 시트보기 (PDF) - Analog Devices

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AD73460
(Rev.:Rev0)

Six-Input Channel Analog Front End

Analog Devices 

AD73460

PIN FUNCTION DESCRIPTIONS1 (continued)

Mnemonic

WR

IRQ2/

PF7

IRQL0/

PF6

IRQL1/

PF5

IRQE/

PF4

Mode D/

PF3

Mode C/

PF2

Mode B/

PF1

Mode A/

PF0

CLKIN,

XTAL

CLKOUT

SPORT0

SPORT1

IRQ1:0

FI

FO

PWD

PWDACK

FL0, FL1,

FL2

A13 to A0

D23 to D0

VDD and

GND

EZ-ICE Port

ERESET

EMS

EE

ECLK

ELOUT

ELIN

EINT

EBR

EBG

Function

(Output) Memory Write Enable Output

(Input) Edge- or Level-Sensitive Interrupt

(Input/Output) Request.2 Programmable I/O Pin

(Input) Level-Sensitive Interrupt Requests2

(Input/Output) Programmable I/O Pin

(Input) Level-Sensitive Interrupt Requests2

(Input/Output) Programmable I/O Pin

(Input) Edge-Sensitive Interrupt Requests2

(Input/Output) Programmable I/O Pin

(Input) Mode Select Input—Checked Only During RESET

(Input/Output) Programmable I/O Pin During Normal Operation

(Input) Mode Select Input—Checked Only During RESET

(Input/Output) Programmable I/O Pin During Normal Operation

(Input) Mode Select Input—Checked Only During RESET

(Input/Output) Programmable I/O Pin During Normal Operation

(Input) Mode Select Input—Checked Only During RESET

(Input/Output) Programmable I/O Pin During Normal Operation

(Inputs) Clock or Quartz Crystal Input

(Output) Processor Clock Output

(Inputs/Outputs) Serial Port I/O Pins

(Inputs/Outputs) Serial Port I/O Pins

(Inputs) Edge- or Level-Sensitive Interrupts,

(Input) Flag In3

(Output) Flag Out3

(Input) Power-Down Control Input

(Output) Power-Down Control Output

(Outputs) Output Flags

(Output) Address Output Pins for Program, Data, Byte, and I/O Space

(Input/Output) Data I/O Pins for Program, Data, Byte, and I/O Space

Power and Ground

(Inputs/Outputs) For Emulation Use

NOTES

1Refer to the ADSP-2185L data sheet for a detailed description of the DSP pins.

2Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the DSP will vector to the appropriate interrupt

vector address when the pin is asserted, either by external devices, or set as a programmable flag.

3SPORT configuration determined by the DSP System Control Register. Software configurable.

REV. 0

–9–

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