AD671JD-750 데이터 시트보기 (PDF) - Analog Devices
부품명
상세내역
일치하는 목록
AD671JD-750 Datasheet PDF : 16 Pages
| |||
AD671–SPECIFICATIONS
DIGITAL SPECIFICATIONS (For all grades TMIN to TMAX, with VCC = +5 V ؎ 5%, VLOGIC = +5 V ؎ 10%, VEE = –5 V
؎ 5%, VREF = +5.000 V, unless otherwise noted)
Parameter
Symbol
Min
Typ
Max
Units
LOGIC INPUT
High Level Input Voltage
VIH
Low Level Input Voltage
VIL
High Level Input Current (VIN = VLOGIC)
IIH
Low Level Input Current (VIN = 0 V)
IIL
Input Capacitance
CIN
+2.0
–10
–10
5
V
+0.8
V
+10
µA
+10
µA
pF
LOGIC OUTPUTS
High Level Output Voltage (IOH = 0.5 mA)
VOH
+2.4
V
Low Level Output Voltage (IOL = 1.6 mA)
VOL
+0.4
V
OSWITCHINGBSPECIFICASTIONS OLETE OutputCapacitance
COUT
5
pF
Specifications shown in boldface are tested on all devices at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max
specifications are guaranteed, although only those shown in boldface are tested.
Specifications subject to change without notice.
Parameter
Conversion Time
(AD671-500)
(AD671-750)
ENCODE Pulse Width High
(AD671-500)
(AD671-750)
ENCODE Pulse Width Low
(For all grades TMIN to TMAX with VCC = +5 V ؎ 5%, VLOGIC = +5 V ؎ 10%, VEE = –5 V
؎ 5%, VIL = 0.8 V, VIH = 2.0 V, VOL = 0.4 V and VOH = 2.4 V)
Symbol
Min
Typ
Max
Units
tC
tC
tENC
tENC
tENCL
475
500
ns
725
750
ns
20
30
ns
20
50
ns
20
ns
DAV Pulse Width
(AD671-500)
(AD671-750)
tDAV
75
tDAV
75
200
ns
300
ns
ENCODE Falling Edge Delay
tF
0
ns
Start New Conversion Delay
tR
0
ns
Data and OTR Delay from DAV Falling Edge
tDD1
20
75
ns
Data and OTR Valid before DAV Rising Edge
tSS2
20
75
ns
NOTES
1tDD is measured from when the falling edge of DAV crosses 0.8 V to when the output crosses 0.4 V or 2.4 V with a 25 pF load capacitor on each output pin.
2tSS is measured from when the outputs cross 0.4 V or 2.4 V to when the rising edge of DAV crosses 2.4 V with a 25 pF load capacitor on each output pin.
a. Encode Pulse HIGH
b. Encode Pulse LOW
Figure 1. AD671 Timing Diagrams
–4–
REV. B
Share Link: 