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AD670BD

Low Cost Signal Conditioning 8-Bit ADC

Analog Devices 

AD670

6b. Bipolar

Figure 7. Control Logic Block Diagram

Table II. AD670 Control Signal Truth Table

R/W CS CE OPERATION

6c. Full Scale (Unipolar)

Figure 6. Transfer Curves

CONTROL AND TIMING OF THE AD670

Control Logic

The AD670 contains on-chip logic to provide conversion and

data read operations from signals commonly available in micro-

processor systems. Figure 7 shows the internal logic circuitry of

the AD670. The control signals, CE, CS, and R/W control the

operation of the converter. The read or write function is deter-

mined by R/W when both CS and CE are low as shown in

Table II. If all three control inputs are held low longer than the

conversion time, the device will continuously convert until one

input, CE, CS, or R/W is brought high. The relative timing of

these signals is discussed later in this section.

0

0

0

WRITE/CONVERT

1

0

0

READ

X

X

1

NONE

X

1

X NONE

Timing

The AD670 is easily interfaced to a variety of microprocessors

and other digital systems. The following discussion of the timing

requirements of the AD670 control signals will provide the de-

signer with useful insight into the operation of the device.

Write/Convert Start Cycle

Figure 8 shows a complete timing diagram for the write/convert

start cycle. CS (chip select) and CE (chip enable) are active low

and are interchangeable signals. Both CS and CE must be low

for the converter to read or start a conversion. The minimum

pulse width, tW, on either CS or CE is 300 ns to start a

conversion.

Table III. AD670 TIMING SPECIFICATIONS

Symbol Parameter

@ +25؇C

Min Typ Max Units

WRITE/CONVERT START MODE

tW

Write/Start Pulse Width

300

tDS

Input Data Setup Time

200

tDH

Input Data Hold

10

tRWC

Read/Write Setup Before Control 0

tDC

Delay to Convert Start

tC

Conversion Time

ns

ns

ns

ns

700 ns

10

µs

READ MODE

tR

Read Time

250

ns

tSD

Delay from Status Low to Data Read

250 ns

tTD

Bus Access Time

200 250 ns

tDH

Data Hold Time

25

ns

tDT

Output Float Delay

150 ns

tRT

R/W before CE or CS low

0

ns

Boldface indicates parameters tested 100% unless otherwise noted. See Specifications page for explanation.

REV. A

–7–

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