AD6672(Rev0) 데이터 시트보기 (PDF) - Analog Devices

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AD6672
(Rev.:Rev0)

IF Receiver

Analog Devices 

TIMING SPECIFICATIONS

Table 5.

Parameter

SPI TIMING REQUIREMENTS

tDS

tDH

tCLK

tS

tH

tHIGH

tLOW

tEN_SDIO

tDIS_SDIO

Test Conditions/Comments

See Figure 42 for the SPI timing diagram

Setup time between the data and the rising edge of SCLK

Hold time between the data and the rising edge of SCLK

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

Minimum period that SCLK should be in a logic high state

Minimum period that SCLK should be in a logic low state

Time required for the SDIO pin to switch from an input to an output

relative to the SCLK falling edge (not shown in Figure 42)

Time required for the SDIO pin to switch from an output to an input

relative to the SCLK rising edge (not shown in Figure 42)

AD6672

Min Typ Max Unit

2

ns

2

ns

40

ns

2

ns

2

ns

10

ns

10

ns

10

ns

10

ns

Rev. 0 | Page 9 of 32

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