AD5764RBSUZ-REEL7 데이터 시트보기 (PDF) - Analog Devices
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AD5764RBSUZ-REEL7
Analog Devices
AD5764RBSUZ-REEL7 Datasheet PDF : 32 Pages
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Preliminary Technical Data
AD5764R
TIMING CHARACTERISTICS
AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 5 V external;
DVCC = 2.7 V to 5.25 V, RLOAD = 10 kΩ, CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1, 2, 3
t1
t2
t3
t4
t5 4
t6
t7
t8
t9
Limit at TMIN, TMAX
33
13
13
13
13
40
2
5
1.4
400
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
μs min
ns min
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24th SCLK falling edge to SYNC rising edge
Minimum SYNC high time
Data setup time
Data hold time
SYNC rising edge to LDAC falling edge (all DACs updated)
SYNC rising edge to LDAC falling edge (single DAC updated)
t10
t11
t12
t13
t14
t155, 6
t16
t17
t18
10
ns min
LDAC pulse width low
500
ns max LDAC falling edge to DAC output response time
10
μs max DAC output settling time
10
ns min
CLR pulse width low
2
μs max CLR pulse activation time
25
ns max SCLK rising edge to SDO valid
20
ns min
SYNC rising edge to SCLK rising edge
2
μs min
SYNC rising edge to DAC output response time (LDAC = 0)
170
ns min
LDAC falling edge to SYNC rising edge
1 Guaranteed by design and characterization; not production tested.
2 All input signals are specified with tr = tf = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3 See Figure 2, Figure 3, and Figure 4.
4 Standalone mode only.
5 Measured with the load circuit of Figure 5.
6 Daisy-chain mode only.
Rev. PrA | Page 7 of 32
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