AD5762RCSUZ-REEL7 데이터 시트보기 (PDF) - Analog Devices

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AD5762RCSUZ-REEL7

Complete Dual, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC

Analog Devices 

AD5762R

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications..................................................................................... 4

AC Performance Characteristics ................................................ 6

Timing Characteristics ................................................................ 7

Absolute Maximum Ratings.......................................................... 10

Thermal Resistance .................................................................... 10

ESD Caution................................................................................ 10

Pin Configuration and Function Descriptions........................... 11

Typical Performance Characteristics ........................................... 13

Terminology .................................................................................... 19

Theory of Operation ...................................................................... 21

DAC Architecture....................................................................... 21

Reference Buffers........................................................................ 21

Serial Interface ............................................................................ 21

Simultaneous Updating via LDAC........................................... 22

Transfer Function ....................................................................... 23

Asynchronous Clear (CLR)....................................................... 23

Registers ........................................................................................... 24

REVISION HISTORY

6/2016—Rev. C to Rev. D

Changes to Table 7 and Table 8..................................................... 23

9/2011—Rev. B to Rev. C

Changed 50 MHz to 30 MHz Throughout.................................... 1

Changes to t1, t2, and t3 Parameters, Table 3 .................................. 7

7/2011—Rev. A to Rev. B

Changed 30 MHz to 50 MHz Throughout.................................... 1

Changes to t1, t2, and t3 Parameters, Table 3 .................................. 7

Data Sheet

Function Register ....................................................................... 24

Data Register ............................................................................... 25

Coarse Gain Register ................................................................. 25

Fine Gain Register ...................................................................... 25

Offset Register ............................................................................ 26

Offset and Gain Adjustment Worked Example ......................... 26

Design Features............................................................................... 27

Analog Output Control ............................................................. 27

Digital Offset and Gain Control............................................... 27

Programmable Short-Circuit Protection ................................ 27

Digital I/O Port........................................................................... 27

Die Temperature Sensor ............................................................ 27

Local Ground Offset Adjust...................................................... 27

Applications Information .............................................................. 28

Typical Operating Circuit ......................................................... 28

Layout Guidelines........................................................................... 30

Galvanically Isolated Interface ................................................. 30

Microprocessor Interfacing....................................................... 30

Evaluation Board ........................................................................ 31

Outline Dimensions ....................................................................... 32

Ordering Guide .......................................................................... 32

8/2009—Rev. 0 to Rev. A

Deleted Endnote 1, Table 1 ..............................................................4

Deleted Endnote 1, Table 2 ..............................................................6

Deleted Endnote 1, Table 3 ..............................................................7

Changes to t6 Parameter, Table 3 .....................................................7

12/2008—Revision 0: Initial Version

Rev. D | Page 2 of 32

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