AD5678BRUZ-2(RevA) 데이터 시트보기 (PDF) - Analog Devices
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AD5678BRUZ-2
(Rev.:RevA)
(Rev.:RevA)
Analog Devices
AD5678BRUZ-2 Datasheet PDF : 28 Pages
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AD5678
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SYNC 1
VDD 2
VOUTA 3
VOUTC 4
VOUTE 5
VOUTG 6
VREFIN/VREFOUT 7
AD5678
TOP VIEW
(Not to Scale)
14 SCLK
13 DIN
12 GND
11 VOUTB
10 VOUTD
9 VOUTF
8 VOUTH
Figure 3. 14-Lead TSSOP (RU-14)
LDAC 1
SYNC 2
VDD 3
VOUTA 4
VOUTC 5
VOUTE 6
VOUTG 7
VREFIN/VREFOUT 8
16 SCLK
15 DIN
AD5678
TOP VIEW
(Not to Scale)
14 GND
13 VOUTB
12 VOUTD
11 VOUTF
10 VOUTH
9 CLR
Figure 4. 16-Lead TSSOP (RU-16)
Table 6. Pin Function Descriptions
Pin No.
14-Lead 16-Lead
TSSOP TSSOP Mnemonic
–
1
LDAC
1
2
SYNC
2
3
VDD
3
4
VOUTA
11
13
VOUTB
4
5
VOUTC
10
12
VOUTD
7
8
VREFIN/VREFOUT
–
9
CLR
5
6
VOUTE
9
11
VOUTF
6
7
VOUTG
8
10
VOUTH
12
14
GND
13
15
DIN
14
16
SCLK
Description
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have
new data. This allows all DAC outputs to simultaneously update. Alternatively, this pin can be
tied permanently low.
Active Low Control Input. This is the frame synchronization signal for the input data. When
SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register.
Data is transferred in on the falling edges of the next 32 clocks. If SYNC is taken high before
the 32nd falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is
ignored by the device.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should
be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
The AD5678 has a common pin for reference input and reference output. When using the
internal reference, this is the reference output pin. When using an external reference, this is
the reference input pin. The default for this pin is as a reference input.
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC
pulses are ignored. When CLR is activated, the input register and the DAC register are
updated with the data contained in the CLR code register—zero, midscale, or full scale.
Default setting clears the output to 0 V.
Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on
the falling edge of the serial clock input.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial
clock input. Data can be transferred at rates of up to 50 MHz.
Rev. A | Page 10 of 28
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