AD5429YRU 데이터 시트보기 (PDF) - Analog Devices

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AD5429YRU

Dual 8-,10-,12-Bit High Bandwidth Multiplying DACs with Serial Interface

Analog Devices 

AD5429/AD5439/AD5449

SCLK

SYNC

DIN

LDAC1

LDAC2

t8

t4

DB15

t6

t5

t1

t2

t3

t7

DB0

t10

t9

t11

NOTES

1ASYNCHRONOUS LDAC UPDATE MODE

2SYNCHRONOUS LDAC UPDATE MODE

ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS

DETERMINED BY CONTROL BITS. TIMING AS ABOVE, WITH SCLK INVERTED.

Figure 2. Standalone Mode Timing Diagram

SCLK

SYNC

SDIN

SDO

t4

DB15

(N)

t6

t5

t1

t2

t3

DB0

(N)

t12

DB15

(N+1)

DB15

(N)

ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS

DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING

EDGE OF SCLK. TIMING AS ABOVE, WITH SCLK INVERTED.

Figure 3. Daisy-Chain and Readback Modes Timing Diagram

t7

t8

DB0

(N+1)

DB0

(N)

200µA

IOL

TO OUTPUT

PIN CL

50pF

VOH (MIN) + VOL (MAX)

2

200µA

IOH

Figure 4. Load Circuit for SDO Timing Specifications

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