AD5426 데이터 시트보기 (PDF) - Analog Devices
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AD5426 Datasheet PDF : 24 Pages
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AD5426/AD5432/AD5443
TIMING CHARACTERISTICS1
(VDD = 3 V to 5.5 V, VREF = 10 V, IOUT2 = O V. All specifications TMIN to TMAX, unless otherwise noted.)
Parameter
3.0 V to 5.5 V 4.5 V to 5.5 V
Unit
Conditions/Comments
fSCLK
50
50
t1
20
20
t2
8
8
t3
8
8
t42
13
13
t5
5
5
t6
3
3
t7
5
5
t8
30
30
t93
80
45
120
65
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns max
Max clock frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK active edge setup time
Data setup time
Data hold time
SYNC rising edge to SCLK active edge
Minimum SYNC high time
SCLK active edge to SDO valid
NOTES
1See Figures 1 and 2. Temperature range is as follows: Y version: –40°C to +125°C. Guaranteed by design and characterization, not subject to production test.
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2Falling or rising edge as determined by control bits of serial word.
3Daisy-chain and readback modes cannot operate at max clock frequency. SDO timing specifications measured with load circuit as shown in Figure 3.
Specifications subject to change without notice.
SCLK
SYNC
DIN
t8
t4
DB15
t6
t5
t1
t2
t3
t7
DB0
ALTERNATIVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF
SCLK AS DETERMINED BY CONTROL BITS. TIMING AS PER ABOVE, WITH SCLK INVERTED.
Figure 1. Standalone Mode Timing Diagram
SCLK
SYNC
SDIN
SDO
t4
DB15 (N)
t6
t5
t1
t2
t3
DB0 (N)
t9
DB15
(N+1)
DB15(N)
ALTERNATiVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING
EDGE OF SCLK. TIMING AS PER ABOVE, WITH SCLK INVERTED.
Figure 2. Daisy-chain and Readback Modes Timing Diagram
t7
t8
DB0 (N+1)
DB0(N)
–4–
REV. 0
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