AD5227 데이터 시트보기 (PDF) - Analog Devices
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AD5227 Datasheet PDF : 16 Pages
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The change of VWB is known provided that the AD5227 has not
reached the maximum or minimum scale. If one ignores the
effect of the wiper resistance, the transfer functions can be
simplified as
ΔVWB
=
+
CP
64
VA
U/D = 1
(3)
ΔVWB
=
−
CP
64
V
A
U/D = 0
(4)
Unlike rheostat mode operation where the absolute tolerance is
high, potentiometer mode operation yields an almost ratiometric
function of CP/64 with a relatively small error contributed by
the RW term. The tolerance effect is, therefore, almost canceled.
Although the thin film step resistor, RS, and CMOS switches
resistance, RW, have very different temperature coefficients, the
ratiometric adjustment also reduces the overall temperature
coefficient to 5 ppm/°C except at low value codes where RW
dominates.
Potentiometer mode operation includes an op amp gain
configuration among others. The A, W, and B terminals can be
input or output terminals and have no polarity constraint
provided that |VAB|, |VWA|, and |VWB| do not exceed VDD-to-GND.
DIGITAL INTERFACE
The AD5227 contains a 3-wire serial input interface. The three
inputs are clock (CLK), chip select (CS), and up/down control
(U/D). These inputs can be controlled digitally for optimum
speed and flexibility
When CS is pulled low, a clock pulse increments or decrements
the up/down counter. The direction is determined by the state
of the U/D pin. When a specific state of the U/D remains, the
device continues to change in the same direction under con-
secutive clocks until it comes to the end of the resistance
setting. All digital inputs, CS, CLK, and U/D pins, are protected
with a series input resistor and a parallel Zener ESD structure as
shown in Figure 28.
1kΩ
LOGIC
Figure 28. Equivalent ESD Protection Digital Pins
TERMINAL VOLTAGE OPERATION RANGE
The AD5227 is designed with internal ESD protection diodes
(Figure 29), but the diodes also set the boundary of the terminal
AD5227
operating voltages. Voltage present on Terminal A, B, or W that
exceeds VDD by more than 0.5 V is clamped by the diode and,
therefore, elevates VDD. There is no polarity constraint between
VAB, VWA, and VWB, but they cannot be higher than VDD-to-
GND.
POWER-UP AND POWER-DOWN SEQUENCES
Because of the ESD protection diodes, it is important to power
on VDD before applying any voltage to Terminals A, B, and W.
Otherwise, the diodes are forward-biased such that VDD can be
powered unintentionally and can affect the rest of the system
circuit. Similarly, VDD should be powered down last. The ideal
power-on sequence is in the following order: GND, VDD, VA/B/W,
and digital inputs.
VDD
A
W
B
GND
Figure 29. Maximum Terminal Voltages Set by VDD and GND
LAYOUT AND POWER SUPPLY BIASING
It is a good practice to use compact, minimum lead length
layout design. The leads to the input should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance. It is also good
practice to bypass the power supplies with quality capacitors.
Low ESR (equivalent series resistance) 1 μF to 10 μF tantalum
or electrolytic capacitors should be applied at the supplies to
minimize any transient disturbance and filter low frequency
ripple.
Figure 30 illustrates the basic supply bypassing configuration
for the AD5227. The ground pin of the AD5227 is a digital
ground reference that should be joined to the common ground
at a single point to minimize the digital ground bounce.
VDD + C2
10μF
C1
0.1μF
AD5227
VDD
GND
Figure 30. Power Supply Bypassing
Rev. B | Page 11 of 16
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