AD1988B 데이터 시트보기 (PDF) - Analog Devices
부품명
상세내역
일치하는 목록
AD1988B Datasheet PDF : 20 Pages
| |||
AD1988A/AD1988B
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DVCORE 1
GPIO_0/VOLUME 2
DVI/O 3
DVSS 4
SDATA_OUT 5
BIT_CLK 6
DVSS 7
SDATA_IN 8
DVDD 9
SYNC 10
RESET 11
PCBEEP 12
PIN 1
INDICATOR
AD1988A/AD1988B
TOP VIEW
(Not to Scale)
36 PORT-D_R
35 PORT-D_L
34 SENSE_B/SRC_A
33 MIC_BIAS_FILT
32 MIC_BIAS/EAPD-D
31 MIC_BIAS-E
30 MIC_BIAS-F
29 MIC_BIAS/EAPD-C
28 MIC_BIAS-B
27 VREF_FILT
26 AVSS
25 AVDD
48 47 46 45 44 43 42 41 40 39 38 37
DVCORE 1
GPIO_0/VOLUME 2
DVI/O 3
DVSS 4
SDATA_OUT 5
BIT_CLK 6
DVSS 7
SDATA_IN 8
DVDD 9
SYNC 10
RESET 11
PCBEEP 12
PIN 1
AD1988A/AD1988B
TOP VIEW
(Not to Scale)
13 14 15 16 17 18 19 20 21 22 23 24
36 PORT-D_R
35 PORT-D_L
34 SENSE_B/SRC_A
33 MIC_BIAS_FILT
32 MIC_BIAS/EAPD-D
31 MIC_BIAS-E
30 MIC_BIAS-F
29 MIC_BIAS/EAPD-C
28 MIC_BIAS-B
27 VREF_FILT
26 AVSS
25 AVDD
Figure 2. LFCSP_VQ Pin Configuration
Figure 3. LFQP Pin Configuration
Table 5. Pin Function Descriptions
Mnemonic
Pin
Number I/O
DVCORE
1
O
GPIO_0/VOLUME
2
I/O
DVIO
DVSS
SDATA_OUT
3
I
4, 7
I
5
I
BIT_CLK
SDATA_IN
6
O
8
I/O
DVDD
9
I
SYNC
10
I
RESET
11
I
PCBEEP
12
I
SENSE_A/SRC_B
13
I/O
PORT-E_L, PORT-E_R 14, 15 I/O
PORT-F_L, PORT-F_R 16, 17 I/O
CD_L, CD_R
18, 20
I
CD_GND
19
I
PORT-B_L, PORT-B_R 21, 22 I/O
Description
Filter Connection for Internal Core Voltage Regulator. This pin must be connected to filter
capacitors: 10 μF, 1.0 μF, and 0.1 μF connected in parallel between Pin 1 and DVSS (Pin 4 and Pin 7).
General-Purpose Input/Output Pin (Digital I/O). Digital signal used to control external circuitry.
Volume Control. When enabled, it can be used as an external volume control
Link Digital I/O Voltage Reference. 3.3 V (±10%).
Digital Supply Return (Ground).
Link Serial Data Output (Digital Interface). AD1988 input stream. Clocked on both edges of the
BIT_CLK.
Link Bit Clock (Digital Interface). 24.000 MHz serial data clock.
Link Serial Data Input (Digital Interface). AD1988 output stream. Clocked only on one edge of
BIT_CLK.
Digital Supply Voltage 3.3 V ± 10%. This is regulated down to 1.9 V on Pin 1 to supply the internal
digital core internal to the AD1988.
Link Frame Sync (Digital Interface). 48 kHz frame sync plus SDI stream IDs.
Link Reset (Digital Interface). AD1988 master hardware reset.
Monaural Input from System for PCBEEP. Line level input.
Jack Sense A to Jack Sense D Input/Sense B Drive.
Left and Right Rear Panel Stereo Mic In/C/LFE (Analog Input/Output).
Input: line level input, supports microphones with MIC_BIAS and boost amplifiers.
Output: line level output.
Left and Right Rear Panel Stereo Mic In/Surround Rear (Analog Input/Output).
Input: line level input, supports microphones with MIC_BIAS and boost amplifiers.
Output: line level output only.
CD Audio Left Channel, CD Audio Right Channel.
CD Audio Analog Ground Reference (for Analog CD Input). Line level input only.
Front Panel Stereo Mic In/Front Panel Headphones. Analog input/output.
Input: line level input, supports microphones with MIC Bias and boost amplifiers.
Output: line level output, capable of driving headphone load and power.
Rev. 0 | Page 8 of 20
Share Link: 