AD1985 데이터 시트보기 (PDF) - Analog Devices
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AD1985 Datasheet PDF : 48 Pages
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AD1985
TIMING PARAMETERS
Guaranteed over operating temperature range.
Table 14.
Parameter
RESET ACTIVE LOW PULSE WIDTH
RESET INACTIVE TO SDATA_IN OR BIT_CLK ACTIVE DELAY
SYNC ACTIVE HIGH PULSE WIDTH
SYNC LOW PULSE WIDTH
SYNC INACTIVE TO BIT_CLK STARTUP DELAY
BIT_CLK FREQUENCY
BIT_CLK PERIOD
BIT_CLK OUTPUT JITTER1, 2
BIT_CLK HIGH PULSE WIDTH
BIT_CLK LOW PULSE WIDTH
SYNC FREQUENCY
SYNC PERIOD
SETUP TO FALLING EDGE OF BIT_CLK
HOLD FROM FALLING EDGE OF BIT_CLK
BIT_CLK RISE TIME
BIT_CLK FALL TIME
SYNC RISE TIME
SYNC FALL TIME
SDATA_IN RISE TIME
SDATA_IN FALL TIME
SDATA_OUT RISE TIME
SDATA_OUT FALL TIME
END OF SLOT 2 TO BIT_CLK, SDATA_IN LOW
SETUP TO TRAILING EDGE OF RESET (APPLIES TO SYNC, SDATA_OUT)
RISING EDGE OF RESET TO HIGH-Z DELAY
PROPAGATION DELAY
RESET RISE TIME
OUTPUT VALID DELAY FROM RISING EDGE OF BIT_CLK TO SDI VALID
RESET INACTIVE TO BIT_CLK STARTUP DELAY
Symbol
tRST_LOW
tRST2CLK
tSYNC_HIGH
tSYNC_LOW
tSYNC2CLK
tCLK_PERIOD
tCLK_HIGH
tCLK_LOW
tSYNC_PERIOD
tSETUP
tHOLD
tRISECLK
tFALLCLK
tRISESYNC
tFALLSYNC
tRISEDIN
tFALLDIN
tRISEDOUT
tFALLDOUT
tS2_PDOWN
tSETUP2RST
tOFF
tCO
tTRI2ACTV
Min
Typ
Max
Unit
1.0
µs
162.8
ns
1.3
µs
19.5
µs
162.8
ns
12.288
MHz
81.4
ns
750
2000
ps
33
42
48
ns
33
38
48
ns
48.0
kHz
20.8
µs
10
2.5
ns
5
ns
2
4
6
ns
2
4
6
ns
2
4
6
ns
2
4
6
ns
2
4
6
ns
2
4
6
ns
2
4
6
ns
2
4
6
ns
0
1.0
µs
15.0
ns
25.0
ns
15
ns
50
ns
15
ns
25
ns
1 Guaranteed, not tested.
2 Output jitter directly dependent on crystal input jitter; maximum specified for noncrystal operation.
Rev. A | Page 8 of 48
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