AD1883 데이터 시트보기 (PDF) - Analog Devices
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AD1883 Datasheet PDF : 20 Pages
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AD1883
Parameter
POWER SUPPLY
Analog (AVDD) 3.3 V ± 5%
Power Supply Range
Power Dissipation
Supply Current
Digital (DVDD) 3.3 V ± 10%
Power Supply Range
Power Dissipation
Supply Current
Digital (DVCORE) 1.7 through 1.9 V ± 10%
Power Supply Range
Power Dissipation
Supply Current
Digital I/O (DVIO) 3.3 V ± 10%
Power Supply Range
Power Dissipation
Supply Current
Digital I/O (DVIO) 1.5 V ± 5.5%
Power Supply Range
Power Dissipation
Supply Current
Power Supply Rejection (Reference to fS 100 mV p-p Signal @ 1 kHz)1
1 Guaranteed but not tested.
Min
Typ
Max
Unit
3.13
3.30
3.46
V
75.9
mW
23
mA
2.97
3.30
3.63
V
141.9
mW
43
mA
1.615
1.70
61
36
1.995
V
mW
mA
2.97
3.30
3.63
V
3.3
mW
1
mA
1.418
1.50
0.08
0.05
80
1.583
V
mW
mA
dB
HD AUDIO LINK SPECIFICATION
High definition audio signals comply with the High Definition
Audio Specification. Please refer to these specifications at
www.intel.com/standards/hdaudio.
POWER-DOWN STATES
Table 4. Power-Down States
Parameter
Function Node in D0, All Nodes Active
Function Node in D3
Function Node in D31
Codec in RESET
Individual Block Power Savings
DAC Pair Powered Down Saves (Each)
ADC Pair Powered Down Saves (Each)
Mixer Power Control (and Associated Amps) Saves
DM_CLK Powered Down Saves2
MIC_BIAS Powered Down Saves3
IDVDD Typ (1.7 V)
36
15.75
7.5
3
IDVDD Typ (3.3 V)
43
17
7.5
3
IAVDD Typ
23
1
1
3
Unit
mA
mA
mA
mA
4.5
6
4.5
6
0
0
0
0
0
0
5
mA
3
mA
2
mA
1
mA
0.1
mA
1 Maximum power saving mode; Register 0x31FD, Bit 4.
2 Test conditions: 30 pF load, 2.0 MHz frequency, 3.3 V AVDD.
3 Powering down the MIC_BIAS powers down all port MIC_BIAS pins. This disables all microphone bias circuits set to 100% or 50%, setting them to the high-Z state. The
0 V and high-Z states remain unaffected by the MIC_BIAS power state.
Rev. 0 | Page 7 of 20 | April 2008
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