AD1877 데이터 시트보기 (PDF) - Analog Devices
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AD1877 Datasheet PDF : 18 Pages
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DIGITAL I/O
Input Voltage HI (VIH)
Input Voltage LO (VIL)
Input Leakage (IIH @ VIH = 5 V)
Input Leakage (IIL @ VIL = 0 V)
Output Voltage HI (VOH @ IOH = –2 mA)
Output Voltage LO (VOL @ IOL = 2 mA)
Input Capacitance
Min
Typ
2.4
2.4
DIGITAL TIMING (Guaranteed over 0°C to 70°C, DVDD = AVDD = 5 V ± 5%. Refer to Figures 17–19.)
Min
Typ
tCLKIN
CLKIN Period
48
FCLKIN
CLKIN Frequency (1/tCLKIN)
1.28
tCPWL
CLKIN LO Pulsewidth
15
tCPWH
CLKIN HI Pulsewidth
15
tRPWL
RESET LO Pulsewidth
50
tBPWL
BCLK LO Pulsewidth
15
tBPWH
BCLK HI Pulsewidth
15
tDLYCKB
tDLYBLR
CLKIN Rise to BCLK Xmit (Master Mode)
BCLK Xmit to LRCK Transition (Master Mode)
tDLYBWR
BCLK Xmit to WCLK Rise
tDLYBWF
BCLK Xmit to WCLK Fall
tDLYDT
BCLK Xmit to Data/Tag Valid (Master Mode)
tSETLRBS
LRCK Setup to BCLK Sample (Slave Mode)
10
tDLYLRDT
LRCK Transition to Data/TAG Valid (Slave Mode)
No MSB Delay Mode (for MSB Only)
tSETWBS
WCLK Setup to BCLK Sample (Slave Mode)
Data Position Controlled by WCLK Input Mode
10
tDLYBDT
BCLK Xmit to DATA/TAG Valid (Slave Mode)
All Bits Except MSB in No MSB Delay Mode
All Bits in MSB Delay Mode
81
12.288
POWER
Supplies
Voltage, Analog and Digital
Analog Current
Analog Current—Power Down (CLKIN Running)
Digital Current
Digital Current—Power Down (CLKIN Running)
Dissipation
Operation—Both Supplies
Operation—Analog Supply
Operation—Digital Supply
Power Down—Both Supplies (CLKIN Running)
Power Down—Both Supplies (CLKIN Not Running)
Power Supply Rejection (See TPC 5)
1 kHz 300 mV p-p Signal at Analog Supply Pins
20 kHz 300 mV p-p Signal at Analog Supply Pins
Stopband (≥0.55 × FS)—any 300 mV p-p Signal
Min
Typ
4.75
5
35
6
16
13
255
175
80
95
5
76
71
80
AD1877
Max
Unit
V
0.8
V
10
µA
10
µA
V
0.4
V
15
pF
Max
780
20.48
15
15
10
10
10
40
10
Unit
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max
5.25
43
26
20
39
315
215
100
325
Unit
V
mA
µA
mA
µA
mW
mW
mW
µW
µW
dB
dB
dB
REV. A
–3–
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