AD1836 데이터 시트보기 (PDF) - Analog Devices
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AD1836 Datasheet PDF : 18 Pages
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PRELIMINARY TECHNICAL DATA
AD1836–SPECIFICATIONS
TIMING (continued)
Parameter
ADC Serial Port
Normal Modes
tABH
ABCLK Delay High
Min
Max
Unit
max
ns
tABL
ABCLK Delay Low
max
ns
tALS
tABDD
tALRDD
LRCLK Delay
ASDATA Delay
ASDATA Delay
Packed 128, 256 Modes
tABH
ABCLK Delay High
max
ns
max
ns
max
ns
max
ns
tABL
ABCLK Delay Low
max
ns
tALS
tABDD
tALRDD
LRCLK Delay
ASDATA Delay
ASDATA Delay
TDM PACKED AUX, MASTER MODE
tABH
ABCLK Delay High
max
ns
max
ns
max
ns
max
ns
tABL
ABCLK Delay Low
max
ns
tXBH
AUXBCLK Delay High
max
ns
tXBL
AUXBCLK Delay Low
max
ns
tALS
tXLS
tABDD
tALRDD
tDDS
tDDH
tDDS
tDDH
tDXDD
tDXDD
LRCLK Delay
AUXLRCLK Delay
ASDATA Delay
ASDATA Delay
AAUXDATA Setup
AAUXDATA Hold
DSDATA Setup
DSDATA Hold
DAUXDATA Delay
DAUXDATA Delay
max
ns
max
ns
max
ns
max
ns
min
ns
min
ns
min
ns
min
ns
max
ns
max
ns
Comments
From MCLK Rising
256 × fS
512 × fS
768 × fS
From MCLK Rising
256 × fS
512 × fS
768 × fS
From ABCLK Falling
From ABCLK Falling
From ALRCLK Changing
(Left-Justified)
From MCLK Rising
256 × fS
512 × fS
768 × fS
From MCLK Rising
256× fS
512 × fS
768 × fS
From ABCLK Falling
From ABCLK Falling
From ALRCLK Changing
(Left-Justified)
From MCLK Rising
256 × fS
512 × fS
768 × fS
From MCLK Rising
256 × fS
512 × fS
768 × fS
From MCLK Rising
256 × fS
512 × fS
768 × fS
From MCLK Rising
256 × fS
512 × fS
768 × fS
From ABCLK Falling
From ABCLK Falling
From ABCLK Falling
From ALRCLK Changing
(Left-Justified)
To AUXBCLK Rising
From AUXBCLK Rising
To DBCLK Rising
From DBCLK Rising
From AUXBCLK Falling
From AUXLRCLK Changing
(Left-Justified)
–4–
REV. PrC
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