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A8502

Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver

Allegro MicroSystems 

A8502

Wide Input Voltage Range, High Efficiency

Fault Tolerant LED Driver

Functional Description

The A8502 incorporates a current-mode boost controller with

internal DMOS switch, and two LED current sinks. It can be

used to drive two LED strings of up to 12 white LEDs in series,

with current up to 120 mA per string. For optimal efficiency, the C1

output of the boost stage is adaptively adjusted to the minimum

voltage required to power both LED strings. This is expressed by

the following equation:

C2

where

VOUT = max ( VLED1 , VLED2 ) + VREG

(1)

C3

VLEDx is the voltage drop across LED strings 1 and 2, and

VREG is the regulation voltage of the LED current sinks (typi-

C4

cally 0.72 V at the maximum LED current).

VDD

FSET/SYNC

ISET

PWM/EN

Enabling the IC

The IC turns on when a logic high signal is applied on the

PWM/EN pin with a minimum duration of tPWMH for the first

clock cycle, and the input voltage present on the VIN pin is

greater than the 4.35 V necessary to clear the UVLO (VUVLOrise )

threshold. The power-up sequence is shown in figure 2. Before

the LEDs are enabled, the A8502 driver goes through a system

check to determine if there are any possible fault conditions that

might prevent the system from functioning correctly. Also, if the

FSET/SYNC pin is pulled low, the IC will not power-up. More

information on the FSET/SYNC pin can be found in the Sync

section of this datasheet.

Powering up: LED pin short-to-ground check

The VIN pin has a UVLO function that prevents the A8502

from powering-up until the UVLO threshold is reached. After

the VIN pin goes above UVLO, and a high signal is present on

the PWM/EN pin, the IC proceeds to power-up. As shown in

figure 3, at this point the A8502 enables the disconnect switch

and checks if any LEDx pins are shorted to ground and/or are not

used.

The LED detect phase starts when the GATE voltage of the

disconnect switch is equal to VIN – 4.5 V. After the voltage

threshold on the LEDx pins exceeds 120 mV, a delay of between

3000 and 4000 clock cycles is used to determine the status of the

pins. Thus, the LED detection duration varies with the switching

t

Figure 2. Power-up diagram; shows VDD (ch1, 2 V/div.), FSET/SYNC (ch2,

1 V/div.), ISET (ch3, 1 V/div.), and PWM/EN (ch4, 2 V/div.) pins,

time = 200 μs/div.

GATE

GATE = VIN – 4.5 V

C1

LEDx

C2

LED detection period

ISET

C3

C4

PWM/EN

t

Figure 3. Power-up diagram; shows the relationship of an LEDx pin with

respect to the gate voltage of the disconnect switch (if used) during the

LED detect phase, as well as the duration of the LED detect phase for a

switching frequency of 2 MHz; shows GATE (ch1, 5 V/div.), LED (ch2,

500 mV/div.), ISET (ch3, 1 V/div.), and PWM/EN (ch4, 5 V/div.) pins,

time = 500 μs/div.

Allegro MicroSystems, Inc.

11

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

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