A62S7316V-70S 데이터 시트보기 (PDF) - AMIC Technology

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A62S7316V-70S

128K X 16 BIT LOW VOLTAGE CMOS SRAM

AMIC Technology 

Timing Waveforms

Read Cycle 1(1, 2, 4)

Address

DOUT

tRC

tAA

tOH

A62S7316 Series

tOH

Read Cycle 2(1, 2, 3)

Address

CE

HB, LB

OE

DOUT

tRC

tAA

tCLZ5

tACE

tBE

tBLZ5

tOE

tOLZ5

tCHZ5

tBHZ5

tOHZ5

Notes:

1. WE is high for Read Cycle.

2. Device is continuously enabled CE = VIL, HB = VIL and, or LB = VIL.

3. Address valid prior to or coincident with CE and ( HB and, or LB ) transition low.

4. OE = VIL.

5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.

PRELIMINARY (March, 2001, Version 0.2)

7

AMIC Technology, Inc.

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