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A6278

Serial-Input Constant-Current Latched LED Drivers with Open LED Detection

Allegro MicroSystems 

A6278 and

A6279

Serial-Input, Constant-Current Latched

LED Drivers with Open LED Detection

OPERATING CHARACTERISTICS

Characteristic

Symbol

Test Conditions

Min. Typ. Max

Unit

ELECTRICAL CHARACTERISTICS valid at TA = 25°C, VDD = 3.0 to 5.5 V, unless otherwise noted

LOGIC SUPPLY Voltage Range

VDD Operating

3.0

5.0

5.5

V

Undervoltage Lockout

VDD(UV)

VDD = 0.0 → 5.0 V

VDD = 5.0 → 0.0 V

2.4

–

2.85

V

2.15

–

2.55

V

VCE = 0.7 V, REXT = 225 Ω

64.2 75.5 86.8

mA

Output Current (any single output)

IO

VCE = 0.7 V, REXT = 470 Ω

34.1 40.0 45.9

mA

VCE = 0.6 V, REXT = 3900 Ω

4.25

5.0

5.75

mA

Output Current Matching (difference between any two

outputs at the same VCE )

VCE(A) = VCE(B) = 0.7 V, REXT = 225 Ω

–

+1.0 +6.0

%

ΔIO

VCE(A) = VCE(B) = 0.7 V, REXT = 470 Ω

–

+1.0 +6.0

%

VCE(A) = VCE(B) = 0.6 V, REXT = 3900 Ω

–

+1.0 +6.0

%

Output Leakage Current

ICEX

VOH = 15 V

–

1.0

5.0

μA

Logic Input Voltage

VIH

VIL

0.7VDD

–

VDD

V

GND

–

0.3VDD

V

Logic Input Voltage Hysteresis

VIhys All digital inputs

200

–

400

mV

SERIAL DATA OUT Voltage

VOL IOL = 500 μA

VOH IOH = –500 μA

–

–

0.4

V

VDD– 0.4 –

–

V

Input Resistance

OUTPUT ENABLE input, Pull Up

RI

LATCH ENABLE input, Pull Down

150

300

600

kΩ

100

200

400

kΩ

REXT = open, VOE = 5 V

–

–

1.4

mA

IDD(OFF) REXT = 470 Ω, VOE = 5 V

–

–

5.0

mA

LOGIC SUPPLY Current

REXT = 225 Ω, VOE = 5 V

REXT = 3900 Ω, VOE = 0 V

–

–

8.0

mA

–

–

3.0

mA

IDD(ON) REXT = 470 Ω, VOE = 0 V

–

–

18.0

mA

REXT = 225 Ω, VOE = 0 V

–

–

32.0

mA

Thermal Shutdown Temperature

TJTSD Temperature increasing

–

165

–

°C

Thermal Shutdown Hysteresis

TJTSDhys

–

15

–

°C

Open LED Detection Threshold

VCE(ODC) IO > 5 mA, VCE ≥ 0.6 V

–

0.30

–

V

SWITCHING CHARACTERISTICS valid at TA = 25°C, VDD = VIH = 3.0 to 5.5 V, VCE = 0.7 V, VIL = 0 V, REXT = 470 Ω, IO = 40 mA, VLED = 3 V, RLED =

58 Ω, CLED = 10 pF, unless otherwise noted

CLOCK Pulse Width

thigh, tlow

20

–

–

ns

SERIAL DATA IN Setup Time

tSU(D)

10

–

–

ns

SERIAL DATA IN Hold Time

tH(D)

10

–

–

ns

LATCH ENABLE Setup Time

tSU(LE)

20

–

–

ns

LATCH ENABLE Hold Time

tH(LE)

20

–

–

ns

OUTPUT ENABLE Set Up Time

OUTPUT ENABLE Hold Time

tSU(OE)

tH(OE)

Normal Mode

40

–

–

ns

20

–

–

ns

OUTPUT ENABLE Pulse Width

tW(OE)

600

–

–

ns

CLOCK to SERIAL DATA OUT Propagation Delay Time

tP(DO)

30

–

–

ns

OUTPUT ENABLE to OUT0 Propagation Delay Time

tP(OE)

–

75

–

ns

Staggering Delay (between consecutive outputs)

tD

10

20

40

ns

Total Delay Time (15 × tD)

tDtotal

–

300

–

ns

CLOCK Pulse Width

thigh, tlow

20

–

–

ns

SERIAL DATA IN Setup Time

tSU(D)

20

–

–

ns

SERIAL DATA IN Hold Time

tH(D)

20

–

–

ns

LATCH ENABLE Setup Time

tSU(LE)

40

–

–

ns

LATCH ENABLE Hold Time

tH(LE)

20

–

–

ns

OUTPUT ENABLE Set Up Time

OUTPUT ENABLE Hold Time

tSU(OE)

tH(OE)

Test Mode, VDD = 4.5 to 5.5 V

40

–

–

ns

20

–

–

ns

OUTPUT ENABLE Pulse Width*

tW(OE)

2.0

–

–

us

CLOCK to SERIAL DATA OUT Propagation Delay Time

tP(DO)

30

–

–

ns

OUTPUT ENABLE to OUT0 Propagation Delay Time

tP(OE)

–

75

–

ns

Staggering Delay (between consecutive outputs)

tD

10

20

40

ns

Total Delay Time (15 × tD)

tDtotal

–

300

–

ns

Output Fall Time

tf

90% to 10% voltage

–

75

150

ns

Output Rise Time

tr

10% to 90% voltage

–

75

150

ns

*See LED Open Circuit Detection (Test) mode timing diagram.

Allegro MicroSystems, Inc.

4

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

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