A45L9332A 데이터 시트보기 (PDF) - AMIC Technology
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A45L9332A Datasheet PDF : 55 Pages
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A45L9332A Series
Mode Register Filed Table to Program Modes
Register Programmed with MRS
Address A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Function RFU W.B.L
TM
(Note 1) (Note 2)
CAS Latency
BT
Burst Length
Test Mode
A8 A7
Type
0 0 Mode Register Set
01
10
11
Vendor
Use
Only
Write Burst Length
A9
Length
0
Burst
1
Single Bit
CAS Latency
A6 A5 A4 Latency
0 0 0 Reserved
001
-
010
2
011
3
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
Special Mode Register Programmed with SMRS
Burst Type
Burst Length
A3 Type A2 A1 A0 BT=0
BT=1
0 Sequential 0 0 0
1
Reserved
1 Interleave 0 0 1
2
Reserved
010
4
4
011
8
8
1 0 0 Reserved Reserved
1 0 1 Reserved Reserved
1 1 0 Reserved Reserved
1 1 1 256(Full) Reserved
(Note 3)
Address A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Function
X
LC
LM
X
Load Color Load Mask
A6 Function A5 Function
0 Disable 0 Disable
1 Enable 1 Enable
(Note 4)
Power Up Sequence
1. Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200µs.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 may be changed.
The device is now ready for normal operation.
Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.
3. The full column burst (256bit) is available only at Sequential mode of burst type.
4. If LC and LM both high (1), data of mask and color register will be unknown.
PRELIMINARY (October, 2001, Version 0.1)
12
AMIC Technology, Inc.
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