74VHC595 데이터 시트보기 (PDF) - Fairchild Semiconductor

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74VHC595

8-Bit Shift Register with Output Latches

Fairchild Semiconductor 

Pin Descriptions

Pin Names

Description

SER

Serial Data Input

SCK

Shift Register Clock Input

(Active rising edge)

RCK

Storage Register Clock Input

(Active rising edge)

SCLR

Reset Input

G

3-STATE Output Enable Input

(Active LOW)

QA - QH

Q’H

Parallel Data Outputs

Serial Data Output

Timing Diagram

Truth Table

Inputs

SER RCK SCK SCLR G

Function

XXX

XXX

XXX

X H QA thru QH 3-STATE

X L QA thru QH outputs enabled

L L Shift Register cleared

LX↑

Q′H = 0

H L Shift Register clocked

HX ↑

QN = Qn-1, Q0 = SER = L

H L Shift Register clocked

X↑X

QN = Qn-1, Q0 = SER = H

H L Contents of Shift

Register transferred to

output latches

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