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M74VHC594RMTR(2004) 데이터 시트보기 (PDF) - STMicroelectronics

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M74VHC594RMTR
(Rev.:2004)
ST-Microelectronics
STMicroelectronics ST-Microelectronics
M74VHC594RMTR Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
74VHC594
8 BIT SHIFT REGISTER
WITH OUTPUT REGISTER
s HIGH SPEED: tPD = 4.2ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA=25°C
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
) s POWER DOWN PROTECTION ON INPUTS
t(s s SYMMETRICAL OUTPUT IMPEDANCE:
c |IOH| = IOL = 8 mA (MIN)
du s BALANCED PROPAGATION DELAYS:
ro tPLH tPHL
s OPERATING VOLTAGE RANGE:
P VCC(OPR) = 2V to 5.5V
te s PIN AND FUNCTION COMPATIBLE WITH
le 74 SERIES 594
o s IMPROVED LATCH-UP IMMUNITY
bs s LOW NOISE: VOLP = 0.8V (MAX.)
- O DESCRIPTION
t(s) The 74VHC594 is an high speed CMOS 8-BIT
SHIFT REGISTERS fabricated with sub-micron
c silicon gate C2MOS technology.
u This device contains an 8-bit serial-in, parallel-out
d shift register that feeds an 8-bit D-type storage
ro register. Separate clocks and direct overriding
P clear (SCLR, RCLR) are provided for both the shift
te register and the storage register.
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
M74VHC594RMTR
M74VHC594TTR
A serial (QH’) output is provided for cascading
purposes. Both the shift register and storage
register use positive-edge triggered clocks. If the
clocks are connected together, the shift register
state will always be one clock pulse ahead of the
storage register.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
Obsole Figure 1: Pin Connection And IEC Logic Symbols
November 2004
Rev. 5
1/14

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