74VCX38 데이터 시트보기 (PDF) - Fairchild Semiconductor

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74VCX38

Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputs

Fairchild Semiconductor 

AC Electrical Characteristics (Note 5)

Symbol

Parameter

Conditions

VCC

TA 40qC to 85qC Units

Figure

(V)

Min

Max

Number

tPZL,

tPLZ

Propagation Delay

CL 30 pF, RL 500:

3.3 r 0.3

0.6

2.8

2.5 r 0.2

0.8

3.7

Figures

1, 2

1.8 r 0.15 1.0

6.7

ns

CL 15 pF, RL 2k:

1.5 r 0.1

1.0

13.4

1.2

33.5

Figures

3, 4

tOSHL

tOSLH

Output to Output Skew

(Note 6)

CL 30 pF, RL 500:

3.3 r 0.3

2.5 r 0.2

1.8 r 0.15

0.5

0.5

0.75

ns

CL 15 pF, RL 2k:

1.5 r 0.1

1.5

1.2

1.5

Note 5: For CL 50PF, add approximately 300 ps to the 30 pF AC maximum specification.

Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The

specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).

Dynamic Switching Characteristics

Symbol

Parameter

VOLP

Quiet Output Dynamic Peak VOL

VOLV

Quiet Output Dynamic Valley VOL

Conditions

CL 30 pF, VIH VCC, VIL 0V

CL 30 pF, VIH VCC, VIL 0V

VCC

TA 25qC

Units

(V)

Typical

1.8

0.25

2.5

0.6

V

3.3

0.8

1.8

0.25

2.5

0.6

V

3.3

0.8

Capacitance

Symbol

Parameter

CIN

COUT

CPD

Input Capacitance

Output Capacitance

Power Dissipation Capacitance

Conditions

TA 25qC

Typical

VI 0v OR VCC, VCC 1.8V, 2.5V or 3.3V

VI 0V or VCC, VCC 1.8V, 2.5V or 3.3V

VI 0V or VCC, f 10 MHz, VCC 1.8V, 2.5V or 3.3V

6.0

7.0

20.0

Units

pF

pF

pF

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