74VHC02M 데이터 시트보기 (PDF) - STMicroelectronics

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74VHC02M

QUAD 2-INPUT NOR GATE

STMicroelectronics 

®

74VHC02

s HIGH SPEED: tPD = 3.6 ns (TYP.) at VCC = 5V

s LOW POWER DISSIPATION:

ICC = 2 µA (MAX.) at TA = 25 oC

s HIGH NOISE IMMUNITY:

VNIH = VNIL = 28% VCC (MIN.)

s POWER DOWN PROTECTION ON INPUTS

s SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 8 mA (MIN)

s BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s OPERATING VOLTAGE RANGE:

VCC (OPR) = 2V to 5.5V

s PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 02

s IMPROVED LATCH-UP IMMUNITY

s LOW NOISE: VOLP = 0.8V (Max.)

DESCRIPTION

The 74VHC02 is an advanced high-speed CMOS

QUAD 2-INPUT NOR GATE fabricated with

sub-micron silicon gate and double-layer metal

wiring C2MOS technology.

QUAD 2-INPUT NOR GATE

PRELIMINARY DATA

M

(Micro Package)

T

(TSSOP Package)

ORDER CODES :

74VHC02M

74VHC02T

The internal circuit is composed of 3 stages

including buffer output, which provides high noise

immunity and stable output.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface 5V to 3V.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2kV ESD immunity and transient excess

voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

June 1999

1/7

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