74LVX86M 데이터 시트보기 (PDF) - Fairchild Semiconductor
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74LVX86M Datasheet PDF : 5 Pages
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May 1993
Revised March 1999
74LVX86
Low Voltage Quad 2-Input Exclusive-OR Gate
General Description
The LVX86 contains four 2-input exclusive-OR gates. The
inputs tolerate voltages up to 7V allowing the interface of
5V systems to 3V systems.
Features
s Input voltage level translation from 5V to 3V
s Ideal for low power/low noise 3.3V applications
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number Package Number
Package Description
74LVX86M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
74LVX86SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX86MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
A0–A3
B0–B3
O0–O3
Description
Inputs
Inputs
Outputs
© 1999 Fairchild Semiconductor Corporation DS011605.prf
www.fairchildsemi.com
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