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74HC7731

Quad 64-bit static shift register

Philips Electronics 

Philips Semiconductors

Quad 64-bit static shift register

60

handbook, halfpage

CPD

(pF)

40

MLA166

20

0

0

0.2

0.4

0.6

duty factor

Fig.6 CPD as a function of the duty factor.

Product specification

74HC/HCT7731

POWER DISSIPATION INFORMATION

The power dissipation per register operating at the same

frequency is given by:

PD = (CPD x VCC2 x fi) + (CL + VCC2 x fo) + (Ipull-up x VCC)

fi

= clock input frequency

fo

= data output frequency

CL = output load capacitance in pF

VCC = power supply voltage in V.

As PD also depends on the frequency at which the

contents of the internal bits are changing, the value of CPD

is a function of the duty factor (df) being the ration between

data and clock frequency, see Fig.6.

Example:

fi

= 12 MHz

fo

= 3 MHz

CL = 25 pF

VCC = 5 V

df

= 3/12 = 0.25

CPD = 42.5 pF

PD = (42.5 × 52 × 12) + (25 × 52 × 3) = 14625 µW

As the maximum allowable power dissipation in an SO

package at Tamb = 125 °C is 60 mW, it is allowed to apply

4 registers at the same time under these conditions.

PACKAGE OUTLINES

See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.

September 1993

8

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