74F563SJ 데이터 시트보기 (PDF) - Fairchild Semiconductor
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74F563SJ Datasheet PDF : 6 Pages
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Unit Loading/Fan Out
Pin Names
D0–D7
LE
OE
O0–O7
Description
Data Inputs
Latch Enable Input (Active HIGH)
3-STATE Output Enable Input (Active LOW)
3-STATE Latch Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
150/40 (33.3)
Input IIH/IIL
Output IOH/IOL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−3 mA/24 mA (20 mA)
Functional Description
The 74F563 contains eight D-type latches with 3-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the Dn inputs enters the latches. In this condition
the latches are transparent, i.e., a latch output will change
state each time its D input changes. When LE is LOW the
latches store the information that was present on the D
inputs a setup time preceding the HIGH-to-LOW transition
of LE. The 3-STATE buffers are controlled by the Output
Enable (OE) input. When OE is LOW, the buffers are in the
bi-state mode. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
Function Table
Inputs
Internal
OE LE D
Q
H XX
X
H HL
H
H HH
L
H LX
NC
L HL
H
L HH
L
L LX
NC
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
NC = No Change
Output
O
Z
Z
Z
Z
H
L
NC
Function
High Z
High Z
High Z
Latched
Transparent
Transparent
Latched
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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