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74AVC16836ADGV

20-bit registered driver with inverted register enable and Dynamic Controlled Outputs™ (3-State)

Philips Electronics 

Philips Semiconductors

20-bit registered driver with inverted register enable

and Dynamic Controlled Outputs™ (3-State)

Product data

74AVC16836A

FEATURES

• Wide supply voltage range of 1.2 V to 3.6 V

• Complies with JEDEC standard no. 8-1A/5/7.

• CMOS low power consumption

• Input/output tolerant up to 3.6 V

• DCO (Dynamic Controlled Output) circuit dynamically changes

output impedance, resulting in noise reduction without speed

degradation

• Low inductance multiple VCC and GND pins for minimum noise

and ground bounce

• Power off disables 74AVC16836A outputs, permitting Live

Insertion

• Integrated input diodes to minimize input overshoot and

undershoot

• Full PC133 solution provided when used with PCK2509S or

PCK2510S and CBT16292

DESCRIPTION

The 74AVC16836A is a 20-bit universal bus driver. Data flow is

controlled by output enable (OE), latch enable (LE) and clock inputs

(CP).

This product is designed to have an extremely fast propagation

delay and a minimum amount of power consumption.

To ensure the high-impedance state during power up or power down,

OE should be tied to VCC through a pullup resistor (Live Insertion).

A Dynamic Controlled Output (DCO) circuitry is implemented to

support termination line drive during transient. See the graphs on

page 8 for typical curves.

PIN CONFIGURATION

OE 1

Y0 2

Y1 3

GND 4

Y2 5

Y3 6

VCC 7

Y4 8

Y5 9

Y6 10

GND 11

Y7 12

Y8 13

Y9 14

Y10 15

Y11 16

Y12 17

GND 18

Y13 19

Y14 20

Y15 21

VCC 22

Y16 23

Y17 24

GND 25

Y18 26

Y19 27

NC 28

56 CP

55 A0

54 A1

53 GND

52 A2

51 A3

50 VCC

49 A4

48 A5

47 A6

46 GND

45 A7

44 A8

43 A9

42 A10

41 A11

40 A12

39 GND

38 A13

37 A14

36 A15

35 VCC

34 A16

33 A17

32 GND

31 A18

30 A19

29 LE

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.0 ns; CL = 30 pF.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

tPHL/tPLH

Propagation delay

An to Yn

VCC = 1.8 V

VCC = 2.5 V

VCC = 3.3 V

2.4

1.7

1.5

tPHL/tPLH

CI

CPD

Propagation delay

LE to Yn;

CP to Yn

Input capacitance

Power dissipation capacitance per buffer

VCC = 1.8 V

VCC = 2.5 V

VCC = 3.3 V

VI = GND to VCC1

2.7

2.1

1.7

3.8

Outputs enabled

25

Output disabled

6

NOTE:

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;

fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.

SH00159

UNIT

ns

ns

pF

pF

ORDERING INFORMATION

PACKAGES

56-Pin Plastic 0.5 mm pitch TSSOP

56-Pin Plastic 0.4 mm pitch TVSOP

TEMPERATURE

RANGE

–40 to +85 °C

–40 to +85 °C

ORDER CODE

74AVC16836ADGG

74AVC16836ADGV

DRAWING

NUMBER

SOT364-1

SOT481-2

2002 Aug 02

2

853-2211 28696

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