Philips Semiconductors
Latch/flip-flop
Product specification
74ALS373/74ALS374
LOGIC DIAGRAM – 74ALS373
D0
D1
D2
D3
D4
D5
D6
D7
3
4
7
8
13
14
17
18
E 11
D
EQ
D
EQ
D
EQ
D
EQ
D
EQ
D
EQ
D
EQ
D
EQ
OE 1
VCC = Pin 20
GND = Pin 10
2
5
6
9
12
15
16
19
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
SF00256
FUNCTION TABLE – 74ALS373
INPUTS
OUTPUTS
INTERNAL REGISTER
OE
E
Dn
Q0 – Q7
L
H
L
L
L
L
H
H
H
H
L
↓
l
L
L
L
↓
h
H
H
L
L
X
NC
NC
H
L
X
NC
Z
H
H
Dn
Dn
Z
H=
h=
L=
l=
NC=
X=
Z=
↓=
High-voltage level
High state must be present one setup time before the High-to-Low enable transition
Low-voltage level
Low state must be present one setup time before the High-to-Low enable transition
No change
Don’t care
High impedance “off” state
High-to-Low enable transition
OPERATING MODE
Enable and read register
Latch and read register
Hold
Disable outputs
1991 Feb 08
4