74ACT299(1999) 데이터 시트보기 (PDF) - STMicroelectronics
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74ACT299 Datasheet PDF : 13 Pages
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74ACT299
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
1, 19
2, 3
7, 13, 6, 14, 5, 15, 4, 16
8, 17
9
11
12
18
10
20
SYMBOL
S0, S1
G1, G2
A/QA to H/QH
QA’ to QH’
CLEAR
SR
CLOCK
SL
GND
VCC
NAME AND FUNCTION
Mode Select Inputs
3 State Output Enable Inputs (Active LOW)
Parallel Data Inputs or 3 State Parallel Outputs (Bus Driver)
Serial Outputs (Standard Output)
Asynchronous Master Reset Input (Active LOW)
Serial Data Shift Right Input
Clock Input (LOW to HIGH, Edge-triggered)
Serial Data Shift Left Input
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
MO DE
INPUTS
INPUTS/OUTPUTS
O UT PUT S
CLEAR FUNCTION
SE L E C T E D
OUTPUT CLOCK
CONTROL
SERIAL
A/QA H/QH QA’ QH’
S1
S0 G1* G2*
SL
SR
Z
L
H
H
X
X
X
X
X
Z
Z
L
L
CLEAR L
L
X
L
L
X
X
X
L
L
L
L
L
X
L
L
L
X
X
X
L
L
L
L
HOLD H
L
L
L
L
X
X
X
QA0 QH0 QA0 QH0
SHIFT H
RIGHT H
L
H
L
L
L
H
L
L
X
H
H
QGn
H
QGn
X
L
L
QGn
L
QGn
SHIFT H
H
L
L
L
LEFT
H
H
L
L
L
H
X
QBn
H
QBn
H
L
X
QBn
L
QBn
L
LOAD H
H
H
X
X
X
X
a
h
a
h
* When one or both output controls are high, the eight, input/output terminals arethe high impedanc e state: howewer sequential operation or clearing of
the register is not affected.
Z : HIGH IMPEDANCE
Qn0 : THE LEVELOF An BEFORE THE INDICATED STEADYSTATEINPUTCONDITIONS WERE ESTABLISED.
Qnn : THE LEVELOF Qn BEFORETHE MOST RECENTACTIVETRANSITIONINDICATEDBY OR
a,h : THE LEVELOF THE STEADYSTATEINPUTSA, H, RESPECTIVELY.
X : DON’T CARE
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