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74ABT648DB

Octal transceiver/register, inverting (3-State)

Philips Electronics 

Philips Semiconductors

Octal bus transceiver/register, inverting (3-State)

Product specification

74ABT648

FEATURES

• Combines 74ABT245 and 74ABT374 type functions in one device

• Independent registers for A and B buses

• Multiplexed real-time and stored data

• Output capability: +64mA/–32mA

• Power-up 3-state

• Power-up reset

• Live insertion/extraction permitted

• Latch-up protection exceeds 500mA per Jedec Std 17

• ESD protection exceeds 2000 V per MIL STD 883 Method 3015

and 200 V per Machine Model

DESCRIPTION

The 74ABT648 high-performance BiCMOS device combines low

static and dynamic power dissipation with high speed and high

output drive.

The 74ABT648 transceiver/register consists of bus transceiver

circuits with inverting 3-State outputs, D-type flip-flops, and control

circuitry arranged for multiplexed transmission of data directly from

the input bus or the internal registers. Data on the A or B bus will be

clocked into the registers as the appropriate clock pin goes High.

Output Enable (OE) and DIR pins are provided to control the

transceiver function. In the transceiver mode, data present at the

high impedance port may be stored in either the A or B register or

both.

The Select (SAB, SBA) pins determine whether data is stored or

transferred through the device in real–time. The DIR determines

which bus will receive data when the OE is active (Low). In the

isolation mode (OE = High), data from Bus A may be stored in the B

register and/or data from Bus B may be stored in the A register.

Outputs from real-time, or stored registers will be inverted. When an

output function is disabled, the input function is still enabled and

may be used to store and transmit data. Only one of the two buses,

A or B may be driven at a time. The examples on the next page

demonstrate the four fundamental bus management functions that

can be performed with the 74ABT648.

QUICK REFERENCE DATA

SYMBOL

PARAMETER

tPLH

Propagation delay

tPHL

An to Bn or Bn to An

CIN

Input capacitance

CP, S, OE, DIR

CI/O

ICCZ

I/O capacitance

Total supply current

CONDITIONS

Tamb = 25°C; GND = 0V

CL = 50pF; VCC = 5V

VI = 0V or VCC

Outputs disabled;

VO = 0V or VCC

Outputs disabled; VCC =5.5V

TYPICAL

5.9

4

7

110

UNIT

ns

pF

pF

µA

ORDERING INFORMATION

PACKAGES

24-Pin Plastic DIP

24-Pin plastic SO

24-Pin Plastic SSOP Type II

24-Pin Plastic TSSOP Type I

TEMPERATURE RANGE

–40°C to +85°C

–40°C to +85°C

–40°C to +85°C

–40°C to +85°C

OUTSIDE NORTH AMERICA

74ABT648 N

74ABT648 D

74ABT648 DB

74ABT648 PW

NORTH AMERICA

74ABT648 N

74ABT648 D

74ABT648 DB

74ABT648PW DH

DWG NUMBER

SOT222-1

SOT137-1

SOT340-1

SOT355-1

PIN CONFIGURATION

CPAB 1

SAB 2

DIR 3

A0 4

A1 5

A2 6

A3 7

A4 8

A5 9

A6 10

A7 11

GND 12

24 VCC

23 CPBA

22 SBA

21 OE

20 B0

19 B1

18 B2

17 B3

16 B4

15 B5

14 B6

13 B7

PIN DESCRIPTION

PIN NUMBER SYMBOL

FUNCTION

1, 23

2, 22

3

CPAB /

CPBA

SAB / SBA

DIR

A to B clock input / B to A clock

input

A to B select input / B to A select

input

Direction control input

4, 5, 6, 7,

8, 9, 10, 11

20, 19, 18, 17,

16, 15, 14, 13

21

A0 – A7 Data inputs/outputs (A side)

B0 – B7

OE

Data inputs/outputs (B side)

Output enable input (active-Low)

12

GND

Ground (0V)

24

VCC

Positive supply voltage

SA00082

1998 Jun 08

2

853–1613 19516

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