3D3418S-0.25 데이터 시트보기 (PDF) - Data Delay Devices
부품명
상세내역
일치하는 목록
3D3418S-0.25 Datasheet PDF : 7 Pages
| |||
MONOLITHIC 8-BIT
PROGRAMMABLE DELAY LINE
(SERIES 3D3418 – LOW NOISE)
3D3418
FEATURES
PACKAGES
• All-silicon, low-power 3.3V CMOS technology
IN 1 16 VDD
• Vapor phase, IR and wave solderable
• Auto-insertable (DIP pkg.)
• Low ground bounce noise
• Leading- and trailing-edge accuracy
• Increment range: 0.25 through 7.5ns
• Delay tolerance: 1% (See Table 1)
• Temperature stability: ±3% typical (0C-70C)
• Vdd stability: ±1% typical (3.0V-3.6V)
• Static Idd: 1.3ma typical
• Minimum input pulse width: 10% of total
delay
AE 2 15 OUT
SO/P0 3 14 MD
P1 4 13 P7
P2 5 12 P6
P3 6 11 SC
P4 7 10 P5
GND 8 9 SI
3D3418 DIP
3D3418G Gull Wing
IN 1
AE 2
SO/P0 3
P1 4
P2 5
P3 6
P4 7
GND 8
16 VDD
15 OUT
14 MD
13 P7
12 P6
11 SC
10 P5
9 SI
3D3418S SOL
(300 Mil)
• Programmable via 3-wire serial or 8-bit parallel interface For mechanical dimensions, click here.
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3D3418 Programmable 8-Bit Silicon Delay Line product family
IN
Signal Input
consists of 8-bit, user-programmable CMOS silicon integrated
OUT Signal Output
circuits. Delay values, programmed either via the serial or parallel
MD Mode Select
interface, can be varied over 255 equal steps ranging from 250ps
AE Address Enable
to 7.5ns inclusively. Units have a typical inherent (address 0)
P0-P7 Parallel Data Input
delay of 20ns (See Table 1). The input is reproduced at the output
SC Serial Clock
without inversion, shifted in time as per user selection. The
SI
Serial Data Input
3D3418 is CMOS-compatible, and features both rising- and
SO Serial Data Output
falling-edge accuracy.
VDD +3.3 Volts
GND Ground
The all-CMOS 3D3418 integrated circuit has been designed as a
reliable, economic alternative to hybrid TTL programmable delay lines. It is offered in a standard 16-pin
auto-insertable DIP and a space saving surface mount 16-pin SOIC.
TABLE 1: PART NUMBER SPECIFICATIONS
PART
NUMBER
3D3418-0.25
3D3418-0.5
3D3418-1
3D3418-2
3D3418-3
3D3418-4
3D3418-5
3D3418-7.5
DELAYS AND TOLERANCES
Step 0
Step 255 Delay
Delay (ns) Delay (ns) Increment (ns)
19.5 ± 3.0 83.25 ± 4.0
0.25 ± 0.15
19.5 ± 3.0 147.0 ± 4.0
0.50 ± 0.25
19.5 ± 3.0 274.5 ± 5.0
1.00 ± 0.50
20.0 ± 3.5 530.0 ± 6.0
2.00 ± 1.00
20.0 ± 3.5 785.0 ± 8.0
3.00 ± 1.50
20.0 ± 3.5 1040 ± 9.0
4.00 ± 2.00
20.0 ± 3.5 1295 ± 10
5.00 ± 2.50
20.5 ± 3.5 1933 ± 15
7.50 ± 3.75
Max Operating
Frequency
6.25 MHz
3.15 MHz
1.56 MHz
0.78 MHz
0.52 MHz
0.39 MHz
0.31 MHz
0.21 MHz
INPUT RESTRICTIONS
Absolute Max Min Operating
Oper Freq
P.W.
90 MHz
80.0 ns
45 MHz
160.0 ns
22 MHz
320.0 ns
11 MHz
640.0 ns
7.5 MHz
960.0 ns
5.5 MHz
1280.0 ns
4.4 MHz
1600.0 ns
2.9 MHz
2400.0 ns
Absolute Min
Oper P.W.
5.5 ns
11.0 ns
22.0 ns
44.0 ns
66.0 ns
88.0 ns
110.0 ns
165.0 ns
NOTES: Any delay increment between 0.25 and 7.5 ns not shown is also available.
All delays referenced to input pin
2002 Data Delay Devices
Doc #02006
DATA DELAY DEVICES, INC.
1
10/28/02
3 Mt. Prospect Ave. Clifton, NJ 07013
Share Link: 